1、American National StandardDeveloped byfor Information Technology PCI ExpressQueuing Interface - 2(PQI-2)INCITS 507-2016INCITS 507-2016INCITS 507-2016American National Standardfor Information Technology PCI ExpressQueuing Interface - 2(PQI-2)SecretariatInformation Technology Industry CouncilApproved
2、May 27, 2016American National Standards Institute, Inc.AbstractThis standard defines a circular queue interface for transferring information between a PQI host and a PQI device over the PCI Express architecture, and defines a scatter gather list (SGL) format that is used to describe data buffers.App
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14、ement in the use ofthis standard.iContentsPageForeword xiiIntroduction xvi1 Scope . 12 Normative references . 22.1 Normative references overview 22.2 References under development . 22.3 Other references 23 Definitions, symbols, abbreviations, and conventions . 33.1 Definitions . 33.2 Symbols and abb
15、reviations 83.3 Keywords 93.4 Editorial conventions 103.5 Numeric and character conventions . 103.5.1 Numeric conventions 103.5.2 Units of measure . 113.5.3 Byte encoded character strings conventions 123.6 State machine conventions 133.6.1 State machine conventions overview 133.6.2 Transitions 133.6
16、.3 Messages, requests, indications, confirmations, responses, and event notifications . 143.6.4 State machine counters, timers, and variables . 143.6.5 State machine arguments . 143.7 Bit and byte ordering 143.8 Notation for procedure calls . 163.9 Notation for UML figures 173.9.1 Introduction . 173
17、.9.2 Class notation . 183.9.3 Class association relationships notation . 193.9.4 Class aggregation relationships notation 203.9.5 Class generalization relationships notation . 223.9.6 Class dependency relationships notation . 233.9.7 Object notation 234 General concepts . 244.1 ASCII data field requ
18、irements 245 Model . 255.1 General overview . 255.2 PQI classes 275.2.1 PQI domain class 275.2.2 PQI host classes . 275.2.2.1 PQI host classes overview 275.2.2.2 PQI Host class . 295.2.2.3 PQI Host Management Application Client class 295.2.2.4 PQI Host Administrator OQ Information class . 295.2.2.5
19、PQI Host Administrator IQ Information class . 295.2.2.6 PQI Host Operational Application Client Interface class . 305.2.2.7 PQI Host Operational OQ Information class . 305.2.2.8 PQI Host Operational IQ Information class . 305.2.3 PQI device classes . 315.2.3.1 PQI device classes overview . 315.2.3.2
20、 PQI Device class . 34ii5.2.3.3 PD State Machine class 345.2.3.4 PQI Device Management Device Server class . 345.2.3.5 PQI Device Operational Device Server Interface class .345.2.3.6 Administrator OQ CI class . 345.2.3.7 Administrator IQ PI class . 345.2.3.8 Operational OQ CI class . 345.2.3.9 Opera
21、tional IQ PI class . 355.2.3.10 PQI Device Administrator OQ Information class . 355.2.3.11 PQI Device Operational OQ Information class 355.2.3.12 PQI Device Administrator IQ Information class . 365.2.3.13 PQI Device Operational IQ Information class 365.2.4 PQI service delivery subsystem classes . 36
22、5.2.4.1 PQI service delivery subsystem classes overview 365.2.4.2 PQI Service Delivery Subsystem class . 375.2.4.3 PCI Express Fabric class 375.2.4.4 PQI Queue Structure class 375.2.5 Circular queue classes 385.2.5.1 Circular queue classes overview . 385.2.5.2 Circular Queue class . 395.2.5.2.1 Circ
23、ular Queue class overview 395.2.5.2.2 Element Array Address attribute 395.2.5.2.3 PI Address attribute . 395.2.5.2.4 CI Address attribute . 395.2.5.3 Element Array class 395.2.5.3.1 Element Array class overview 395.2.5.3.2 Number Of Elements attribute . 395.2.5.3.3 Element Length attribute 405.2.5.4
24、 Element class 405.2.5.5 PI class 405.2.5.5.1 PI class overview . 405.2.5.5.2 Index attribute 405.2.5.6 CI class . 405.2.5.6.1 CI class overview . 405.2.5.6.2 Index attribute 405.2.5.7 IQ class . 405.2.5.7.1 IQ functional overview . 405.2.5.7.2 Example of IQ object locations that are not separated 4
25、25.2.5.7.3 Example of IQ object locations that are separated 435.2.5.8 Administrator IQ class . 445.2.5.8.1 Administrator IQ class overview 445.2.5.8.2 Element Array Address attribute 445.2.5.8.3 Element Length attribute 445.2.5.8.4 Number Of Elements attribute . 445.2.5.8.5 PI Address attribute . 4
26、45.2.5.8.6 CI Address attribute . 445.2.5.9 Operational IQ class 445.2.5.9.1 Operational IQ class overview . 445.2.5.9.2 IQ ID attribute 445.2.5.9.3 Element Array Address attribute 455.2.5.9.4 Element Length attribute 455.2.5.9.5 Number Of Elements attribute . 455.2.5.9.6 PI Address attribute . 455.
27、2.5.9.7 CI Address attribute . 455.2.5.9.8 Spanning Allowed attribute 455.2.5.9.9 Queue Protocol attribute 465.2.5.9.10 Arbitration Priority attribute 465.2.5.10 OQ class . 46iii5.2.5.10.1 OQ functional overview 465.2.5.10.2 Example of OQ object locations that are not separated 475.2.5.10.3 Example
28、of OQ object locations that are separated 485.2.5.10.4 Interrupt Message Number attribute 495.2.5.10.5 MSI-X Disable attribute 495.2.5.11 Administrator OQ class . 495.2.5.11.1 Administrator OQ class overview . 495.2.5.11.2 Interrupt Message Number attribute 495.2.5.11.3 MSI-X Disable attribute 495.2
29、.5.11.4 Element Array Address attribute 495.2.5.11.5 Element Length attribute 495.2.5.11.6 Number Of Elements attribute . 495.2.5.11.7 PI Address attribute . 505.2.5.11.8 CI Address attribute . 505.2.5.12 Operational OQ class 505.2.5.12.1 Operational OQ class overview . 505.2.5.12.2 OQ ID attribute
30、. 505.2.5.12.3 Element Array Address attribute 505.2.5.12.4 Element Length attribute 505.2.5.12.5 Number Of Elements attribute . 505.2.5.12.6 PI Address attribute . 515.2.5.12.7 CI Address attribute . 515.2.5.12.8 Minimum Coalescing Time attribute 515.2.5.12.9 Maximum Coalescing Time attribute . 515
31、.2.5.12.10 Coalescing Count attribute 515.2.5.12.11 Wait For Rearm attribute . 525.2.5.12.12 Interrupt Message Number attribute 525.2.5.12.13 MSI-X Disable attribute 525.2.5.12.14 Spanning Allowed attribute 525.2.5.12.15 Queue Protocol attribute 525.3 Queuing model . 535.3.1 Queuing model overview 5
32、35.3.2 Circular queue model 535.3.2.1 Circular queue functional overview . 535.3.2.2 Relationship of IU to elements 555.3.2.3 Queue producer 555.3.2.4 Queue consumer . 565.3.2.5 Enqueue operation 565.3.2.5.1 Enqueue To IQ operation overview . 565.3.2.5.2 Enqueue To OQ operation overview . 575.3.2.5.
33、3 PQI host enqueuing IUs to an IQ . 575.3.2.5.4 PQI device enqueuing IUs to an OQ . 585.3.2.6 Dequeue operation 605.3.2.6.1 Dequeue From IQ operation overview . 605.3.2.6.2 Dequeue From OQ operation overview . 605.3.2.6.3 PQI host dequeuing IUs from an OQ . 605.3.2.6.4 PQI device dequeuing IUs from
34、an IQ . 625.3.2.7 IU Available notification . 635.3.2.7.1 IU Available On IQ operation overview 635.3.2.7.2 IU Available On OQ operation overview 635.3.2.7.3 IU Available On OQ notification . 635.3.2.7.4 IU Available On IQ notification . 635.3.3 Creating circular queues . 645.3.3.1 Creating circular
35、 queues overview 645.3.3.2 Creating the administrator queue pair . 645.3.3.3 Creating operational queues . 675.3.4 Deleting circular queues . 68iv5.3.4.1 Deleting circular queues overview . 685.3.4.2 Deleting the administrator queue pair . 685.3.4.3 Deleting operational queues 695.3.5 IQ priority an
36、d IQ arbitration 705.3.5.1 IQ priority and IQ arbitration overview . 705.3.5.2 Arbitration burst . 715.3.5.3 Arbitration priorities . 725.4 OQ service notification methods 745.4.1 OQ service notification methods overview 745.4.2 Sending OQ service notifications in MSI-X mode . 745.4.2.1 Sending OQ s
37、ervice notifications in MSI-X mode overview 745.4.2.2 Sending OQ service notifications for an administrator OQ 745.4.2.3 Sending OQ service notifications for an operational OQ .745.4.3 Sending OQ service notifications in legacy INTx mode 775.4.4 Sending OQ service notifications in polled mode . 785.
38、4.5 Servicing OQ service notifications in MSI-X mode . 785.4.6 Servicing OQ service notifications in legacy INTx mode 785.4.7 Servicing OQ service notifications in polled mode 785.5 PD (PQI device) state machine 795.5.1 PD (PQI device) state machine overview . 795.5.2 PD0:Power_On_And_Reset state 79
39、5.5.2.1 PD0:Power_On_And_Reset state description 795.5.2.2 Transition PD0:Power_On_And_Reset to PD1:PQI_Status_Available . 805.5.3 PD1:PQI_Status_Available state 805.5.3.1 PD1:PQI_Status_Available state description 805.5.3.2 Transition PD1:PQI_Status_Available to PD0:Power_On_And_Reset . 805.5.3.3 T
40、ransition PD1:PQI_Status_Available to PD2:All_Registers_Ready 805.5.3.4 Transition PD1:PQI_Status_Available to PD4:Error 805.5.4 PD2:All_Registers_Ready state 805.5.4.1 PD2:All_Registers_Ready state description 805.5.4.2 Transition PD2:All_Registers_Ready to PD0:Power_On_And_Reset 815.5.4.3 Transiti
41、on PD2:All_Registers_Ready to PD1:PQI_Status_Available 815.5.4.4 Transition PD2:All_Registers_Ready to PD3:Administrator_Queue_Pair_Ready 815.5.4.5 Transition PD2:All_Registers_Ready to PD4:Error . 815.5.5 PD3:Administrator_Queue_Pair_Ready state 815.5.5.1 PD3:Administrator_Queue_Pair_Ready state de
42、scription 815.5.5.2 Transition PD3:Administrator_Queue_Pair_Ready to PD0:Power_On_And_Reset . 815.5.5.3 Transition PD3:Administrator_Queue_Pair_Ready to PD1:PQI_Status_Available . 815.5.5.4 Transition PD3:Administrator_Queue_Pair_Ready to PD2:All_Registers_Ready 825.5.5.5 Transition PD3:Administrato
43、r_Queue_Pair_Ready to PD4:Error 825.5.6 PD4:Error state . 825.5.6.1 PD4:Error state description . 825.5.6.2 Transition PD4:Error to PD0:Power_On_And_Reset 825.5.6.3 Transition PD4:Error to PD1:PQI_Status_Available 825.6 Register based error information 835.7 PQI reset 855.7.1 PQI reset overview . 85
44、5.7.2 PQI soft reset 855.7.3 PQI firm reset 865.7.4 PQI hard reset 866 PCI Express requirements and PQI device registers . 876.1 PCI Express requirements . 876.2 PQI device memory space . 886.2.1 PQI device memory space overview . 886.2.2 PQI device standard registers . 896.2.3 PQI device assigned r
45、egisters 90v6.2.4 PQI Device Signature register 906.2.5 Administrator Queue Configuration Function register . 916.2.6 PQI Device Capability register 926.2.7 Legacy INTx Interrupt Status register . 936.2.8 Legacy INTx Interrupt Mask Set register 946.2.9 Legacy INTx Interrupt Mask Clear register . 946
46、.2.10 PQI Device Status register 956.2.11 Administrator IQ PI Offset register 966.2.12 Administrator OQ CI Offset register 966.2.13 Administrator IQ Element Array Address register . 976.2.14 Administrator OQ Element Array Address register . 976.2.15 Administrator IQ CI Address register 976.2.16 Admi
47、nistrator OQ PI Address register . 986.2.17 Administrator Queue Parameter register 986.2.18 PQI Device Error register 996.2.19 PQI Device Error Details register 1006.2.20 PQI Device Reset register 1016.2.21 PQI Device Power Action register . 1027 Queuing layer . 1067.1 IQ CI, IQ PI, OQ CI, and OQ PI
48、 structures . 1067.1.1 IQ CI dword . 1067.1.2 IQ PI register . 1067.1.3 OQ CI register . 1067.1.4 OQ PI dword . 1078 SGL (scatter gather list) . 1088.1 SGL overview . 1088.2 Standard SGL segment and last standard SGL segment 1088.3 SGL descriptors 1098.3.1 SGL descriptors overview . 1098.3.2 Data Bl
49、ock descriptor 1098.3.3 Bit Bucket descriptor . 1108.3.4 Standard SGL Segment descriptor . 1118.3.5 Last Standard SGL Segment descriptor . 1129 Common properties for all IU layers 1139.1 Overview of common properties for all IU layers 1139.2 IUs and elements . 1139.2.1 IUs and elements overview . 1139.2.2 IU contained within a single element 1139.2.3 IU that spans multiple elements 1139.3 Common IU header for all IU layers . 11410 Administrator IUs and administrator functions . 11610.1 IU definition 11610.1.1 IU definition overview 11610.1.2 Administrator IU header 11710.1.3 NULL IU 1191
