1、American National StandardDeveloped byfor Information Technology AT Attachment 8 ATA/ATAPI Parallel Transport(ATA8-APT)INCITS 524-2016INCITS 524-2016INCITS 524-2016American National Standardfor Information Technology AT Attachment 8 ATA/ATAPI Parallel Transport(ATA8-APT)SecretariatInformation Techno
2、logy Industry CouncilApproved October 11, 2016American National Standards Institute, Inc.AbstractThis standard specifies the AT Attachment Interface between host systems and storage devices using aparallel electrical interface. It provides a common attachment interface for systems manufacturers, sys
3、temintegrators, software suppliers, and suppliers of intelligent storage devices.This standard maintains a high degree of compatibility with the AT Attachment Interface with Packet Inter-face - 7 (ATA/ATAPI-7), INCITS 397-2005, and while providing additional functions, is not intended to re-quire ch
4、anges to presently installed devices or existing software.Approval of an American National Standard requires review by ANSI that therequirements for due process, consensus, and other criteria for approval havebeen met by the standards developer.Consensus is established when, in the judgement of the
5、ANSI Board ofStandards Review, substantial agreement has been reached by directly andmaterially affected interests. Substantial agreement means much more thana simple majority, but not necessarily unanimity. Consensus requires that allviews and objections be considered, and that a concerted effort b
6、e madetowards their resolution.The use of American National Standards is completely voluntary; theirexistence does not in any respect preclude anyone, whether he has approvedthe standards or not, from manufacturing, marketing, purchasing, or usingproducts, processes, or procedures not conforming to
7、the standards.The American National Standards Institute does not develop standards andwill in no circumstances give an interpretation of any American NationalStandard. Moreover, no person shall have the right or authority to issue aninterpretation of an American National Standard in the name of the
8、AmericanNational Standards Institute. Requests for interpretations should beaddressed to the secretariat or sponsor whose name appears on the titlepage of this standard.CAUTION NOTICE: This American National Standard may be revised orwithdrawn at any time. The procedures of the American National Sta
9、ndardsInstitute require that action be taken periodically to reaffirm, revise, orwithdraw this standard. Purchasers of American National Standards mayreceive current information on all standards by calling or writing the AmericanNational Standards Institute.American National StandardPublished byAmer
10、ican National Standards Institute, Inc.25 West 43rd Street, New York, NY 10036Copyright 2016 by Information Technology Industry Council (ITI)All rights reserved.No part of this publication may be reproduced in anyform, in an electronic retrieval system or otherwise,without prior written permission o
11、f ITI, 1101 K Street NW, Suite 610, Washington, DC 20005. Printed in the United States of AmericaCAUTION: The developers of this standard have requested that holders of patents that may berequired for the implementation of the standard disclose such patents to the publisher. However,neither the deve
12、lopers nor the publisher have undertaken a patent search in order to identifywhich, if any, patents may apply to this standard. As of the date of publication of this standardand following calls for the identification of patents that may be required for the implementation ofthe standard, no such clai
13、ms have been made. No further patent search is conducted by the de-veloper or publisher in respect to any standard it processes. No representation is made or impliedthat licenses are not required to avoid infringement in the use of this standard.i Contents Page Foreword xii 1 Scope 1 2 Normative ref
14、erences 3 2.1 References Overview . 3 2.2 Approved references 3 2.2.1 Obtaining references . 3 2.2.2 ISO References . 3 2.2.3 ANSI References . 3 2.3 Other references . 4 3 Definitions, abbreviations, and conventions 5 3.1 Definitions and abbreviations 5 3.2 Acronyms and Abbreviations 6 3.3 Conventi
15、ons 7 3.3.1 Editorial conventions 7 3.3.2 Precedence . 7 3.3.3 Lists . 7 3.3.4 Keywords . 7 3.3.4.1 Keyword Overview . 7 3.3.4.2 expected 7 3.3.4.3 mandatory 7 3.3.4.4 may 7 3.3.4.5 obsolete . 7 3.3.4.6 optional. 8 3.3.4.7 prohibited . 8 3.3.4.8 reserved . 8 3.3.4.9 retired . 8 3.3.4.10 shall 8 3.3.
16、4.11 should . 8 3.3.5 Numbering . 8 3.3.6 Signal conventions. 8 3.3.7 Bit conventions 9 3.3.8 State diagram conventions 9 3.3.9 Timing conventions 10 3.3.10 Byte ordering for data transfers . 11 3.3.11 Byte, word and DWORD Relationships . 12 4 Mapping ATA8-AAM and ATA8-ACS to APT . 13 4.1 ATA8-ACS P
17、arameter Mapping Overview 13 4.1.1 Inputs . 13 4.1.2 Outputs 13 4.1.3 Registers . 13 4.1.4 28-bit Commands and 48-bit Commands for ATA Devices 14 4.1.5 Commands for ATAPI Devices 14 4.2 Common Inputs and Outputs 15 4.2.1 Overview 15 4.2.2 Status Output . 15 4.2.2.1 Status return bits overview . 15 4
18、.2.2.2 BSY bit . 15 4.2.2.3 DRDY bit 16 4.2.2.4 DRQ bit 16 4.2.3 Alternate Status Register Output . 16 4.2.4 Command Input . 16 4.2.5 Error Output . 16 ii 4.2.5.1 Error return overview . 16 4.2.5.2 Interface CRC 17 4.2.6 Interrupt Reason Output 17 4.2.6.1 TAG 17 4.2.6.2 REL 17 4.2.6.3 I/O 17 4.2.6.4
19、 C/D . 17 4.2.7 Device Input and Output 17 4.2.7.1 DEV 17 4.2.8 Device Control Register . 18 4.2.8.1 Overview 18 4.2.8.2 HOB (High Order Bit) . 18 4.2.8.3 SRST bit . 18 4.2.8.4 nIEN bit 18 4.3 28-bit Command Inputs and Outputs 19 4.3.1 Feature Input . 19 4.3.2 Count Input and Output . 19 4.3.3 LBA I
20、nput and Output 19 4.3.4 Command Input and Status Output Value Mapping 19 4.4 48-bit Command Inputs and Outputs 20 4.4.1 Feature Input . 20 4.4.2 Count Input and Output Value . 20 4.4.3 LBA Input and Output 20 4.5 ATA8-ACS Transport Specific Command Interactions . 22 4.5.1 Overview 22 4.5.2 DEVICE R
21、ESET 22 See 9.11. 22 4.5.3 EXECUTE DEVICE DIAGNOSTIC 22 See 9.10. 22 4.5.4 IDENTIFY PACKET DEVICE 22 4.5.5 SLEEP command and PM3:Sleep state 22 4.6 ATA8-AAM Command Events 22 4.6.1 Command aborted . 22 4.6.2 Command acceptance 22 4.6.3 Command completion . 22 4.7 ATA8-AAM Protocols 23 5 Parallel int
22、erface physical and electrical requirements . 24 5.1 Cable configuration . 24 5.2 Electrical characteristics . 24 5.2.1 AC characteristics measurement techniques 26 5.2.1.1 Slew rate 26 5.2.1.2 VSSO27 5.2.2 Driver types and required termination . 28 5.2.3 Electrical characteristics for Ultra DMA . 2
23、8 5.2.3.1 Cable configuration 28 5.2.3.2 Series termination required for Ultra DMA . 29 5.2.3.3 PCB trace requirements for Ultra DMA 30 5.3 Connectors and cable assemblies 32 5.3.1 40-pin Connector . 32 5.3.1.1 40-conductor cable 35 5.3.1.2 80-conductor cable assembly using the 40-pin connector . 36
24、 5.3.2 4-pin power connector . 42 5.3.2.1 Mating performance . 44 5.3.3 Unitized connectors . 44 5.3.4 50-pin 2.5 inch form factor style connector . 46 5.3.5 CompactFlash connector 48 5.3.6 1.8 inch 3.3V parallel connector 48 5.4 Physical form factors 50 iii 5.4.1 3.5 inch form factor 50 5.4.1.1 Con
25、nector location for 3.5 inch form factor 51 5.4.2 2.5 inch form factor 52 5.4.2.1 Connector location for 2.5 inch form factor 55 5.4.3 1.8 inch PCMCIA form factor . 57 5.4.3.1 Connector location for 1.8 inch PCMCIA form factor . 57 5.4.4 1.8 inch 5V parallel form factor 57 5.4.4.1 Connector location
26、 for 1.8 inch 5V parallel form factor 59 5.4.5 1.8 inch 3.3 V parallel form factor 60 5.4.5.1 Connector location for 1.8 inch 3.3V parallel form factor . 62 5.4.6 5.25 inch form factor 62 5.4.6.1 5.25 inch HDD form factor . 62 5.4.6.2 5.25 inch CD-ROM form factor 63 5.4.6.3 CompactFlash form factor
27、. 65 6 Parallel interface signal assignments and descriptions 66 6.1 Signal summary 66 6.2 Signal descriptions 67 6.2.1 CS(1:0)- (Chip select) . 67 6.2.2 DA(2:0) (Device address) . 67 6.2.3 DASP- (Device active, Device 1 present) 67 6.2.4 DD(15:0) (Device data) . 67 6.2.5 DIOR-:HDMARDY-:HSTROBE (Dev
28、ice I/O read:Ultra DMA ready:Ultra DMA data strobe) . 67 6.2.6 DIOW-:STOP (Device I/O write:Stop Ultra DMA burst) . 67 6.2.7 DMACK- (DMA acknowledge) . 67 6.2.8 DMARQ (DMA request) . 68 6.2.9 INTRQ (Device interrupt) . 68 6.2.10 IORDY:DDMARDY-:DSTROBE (I/O channel ready:Ultra DMA ready:Ultra DMA dat
29、a strobe)68 6.2.11 PDIAG-:CBLID- (Passed diagnostics:Cable assembly type identifier) 68 6.2.12 RESET- (Hardware reset) . 70 6.2.13 CSEL (Cable select) 70 6.2.13.1 CSEL with 40-conductor cable . 70 6.2.13.2 CSEL with 80-conductor cable . 70 7 Parallel interface general operational requirements 72 7.1
30、 Interrupts . 72 7.2 Multiword DMA 72 7.3 Ultra DMA feature set . 73 7.3.1 Overview 73 7.3.2 Phases of operation . 74 7.3.2.1 Ultra DMA burst initiation phase rules 74 7.3.2.2 Data transfer phase rules. 75 7.3.2.3 Ultra DMA burst termination phase rules . 75 7.4 Host determination of cable type by d
31、etecting CBLID- . 75 8 Parallel interface register addressing 78 9 Parallel interface transport protocol 85 9.1 Power-on and hardware reset protocol . 88 9.2 Software reset protocol . 93 9.3 Bus idle protocol . 98 9.4 Non-data command protocol 108 9.5 PIO data-in command protocol . 110 9.6 PIO data-
32、out command protocol . 114 9.7 DMA command protocol . 118 9.8 PACKET command protocol . 121 9.9 DMA QUEUED command protocol . 133 iv 9.10 EXECUTE DEVICE DIAGNOSTIC command protocol 137 9.11 DEVICE RESET command protocol . 142 9.12 Ultra DMA data-in commands. 144 9.12.1 Initiating an Ultra DMA data-i
33、n burst 144 9.12.2 The data-in transfer . 144 9.12.3 Pausing an Ultra DMA data-in burst 145 9.12.3.1 Device pausing an Ultra DMA data-in burst . 145 9.12.3.2 Host pausing an Ultra DMA data-in burst . 145 9.12.4 Terminating an Ultra DMA data-in burst 145 9.12.4.1 Device terminating an Ultra DMA data-
34、in burst 145 9.12.4.2 Host terminating an Ultra DMA data-in burst 146 9.13 Ultra DMA data-out commands 147 9.13.1 Initiating an Ultra DMA data-out burst . 147 9.13.2 The data-out transfer . 148 9.13.3 Pausing an Ultra DMA data-out burst 148 9.13.3.1 Host pausing an Ultra DMA data-out burst . 148 9.1
35、3.3.2 Device pausing an Ultra DMA data-out burst . 148 9.13.4 Terminating an Ultra DMA data-out burst 148 9.13.4.1 Host terminating an Ultra DMA data-out burst 148 9.13.4.2 Device terminating an Ultra DMA data-out burst 149 9.14 Ultra DMA CRC rules 150 10 Parallel interface timing . 153 10.1 Deskewi
36、ng 153 10.2 Transfer timing 153 10.2.1 Register transfers 153 10.2.2 PIO data transfers . 155 10.2.3 Multiword DMA data transfer . 158 10.2.3.1 Initiating a Multiword DMA data burst . 158 10.2.3.2 Sustaining a Multiword DMA data burst 160 10.2.3.3 Device terminating a Multiword DMA data burst 161 10
37、.2.3.4 Host terminating a Multiword DMA data burst 162 10.2.4 Ultra DMA data transfer . 163 10.2.4.1 Initiating an Ultra DMA data-in burst . 166 10.2.4.2 Sustained Ultra DMA data-in burst . 167 10.2.4.3 Host pausing an Ultra DMA data-in burst . 168 10.2.4.4 Device terminating an Ultra DMA data-in bu
38、rst 169 10.2.4.5 Host terminating an Ultra DMA data-in burst 170 10.2.4.6 Initiating an Ultra DMA data-out burst 171 10.2.4.7 Sustained Ultra DMA data-out burst . 172 10.2.4.8 Device pausing an Ultra DMA data-out burst . 173 10.2.4.9 Host terminating an Ultra DMA data-out burst 174 10.2.4.10 Device
39、terminating an Ultra DMA data-out burst 175 ANNEX A. DEVICE DETERMINATION OF CABLE TYPE (INFORMATIVE) 176 A.1 Overview . 176 A.2 Sequence for device detection of installed capacitor 177 A.3 Using the combination of methods for detecting cable type. 178 ANNEX B. SIGNAL INTEGRITY AND UDMA IMPLEMENTATI
40、ON GUIDE (INFORMATIVE) 180 B.1 Introduction 180 B.2 The issues . 180 v B.2.1 Timing . 180 B.2.1.1 Cabling. 181 B.2.1.2 Skew 181 B.2.1.3 Source-terminated bus 182 B.2.1.4 Timing measurements for the 80-conductor cable assembly 187 B.2.1.5 Simulations for the 80-conductor cable assembly . 187 B.2.2 Cr
41、osstalk . 188 B.2.2.1 Capacitive coupling 189 B.2.2.2 Inductive coupling 191 B.2.2.3 Mixed capacitive and inductive coupling 192 B.2.2.4 Crosstalk from distributed coupling . 194 B.2.2.5 Measuring crosstalk in a system . 198 B.2.2.6 System design considerations to minimize crosstalk 198 B.2.3 Ground
42、/Power Bounce 199 B.2.4 Ringing and data settling time (DST) for the 40-conductor cable assembly . 201 B.2.4.1 Controlling ringing on a 40-conductor cable assembly 204 B.2.4.2 STROBE lines on the 40-conductor cable . 206 B.3 System Guidelines for Ultra DMA . 207 B.3.1 System capacitance 207 B.3.2 Pu
43、ll-up and pull-down resistors . 207 B.3.3 Cables and connectors . 207 B.3.4 Host PCB and IC design . 208 B.3.5 Sender and recipient component I/Os. 208 B.4 Ultra DMA electrical characteristics . 209 B.4.1 DC characteristics . 209 B.4.1.1 ViHmaximum . 210 B.4.1.2 VDD3(modes higher than 4 only) 210 B.
44、4.1.3 VoH2minimum and maximum(modes higher than 4 only) 210 B.4.1.4 V+ and V- thresholds(modes higher than 4 only) 210 B.4.1.5 Hysteresis (VHYS)(modes higher than 4 only) . 211 B.4.2 AC characteristics . 211 B.4.2.1 SRISE2and SFALL2(modes higher than 4 only) 211 B.4.2.2 VDSSOand VHSSO(modes higher t
45、han 4 only) . 211 B.4.2.3 Cratio(modes higher than 4 only) 211 B.5 Ultra DMA timing and protocol . 212 B.5.1 Ultra DMA timing assumptions 212 B.5.1.1 System delays and skews . 212 B.5.1.2 IC and PCB timings, delays, and skews 213 B.5.2 Ultra DMA timing parameters 215 B.5.2.1 Typical average two-cycl
46、e time (t2CYCTYP) 215 B.5.2.2 Cycle time (tCYC) . 215 B.5.2.3 -cycle time (t2CYC) . 215 B.5.2.4 Data setup time (tDS) 216 B.5.2.5 Data hold time (tDH) 216 B.5.2.6 Data valid setup time (tDVS) 217 B.5.2.7 Data hold time (tDVH) 217 B.5.2.8 CRC word setup time (tCS) (modes higher than 4 only) . 218 B.5
47、.2.9 CRC word hold time (tCH) (modes higher than 4 only) . 218 B.5.2.10 CRC word valid setup time (tCVS) (modes higher than 4 only) . 218 B.5.2.11 CRC word valid hold time (tCVH) (modes higher than 4 only) . 219 B.5.2.12 First DSTROBE time (tZFS) (modes higher than 4 only) . 219 B.5.2.13 Data enable
48、d to the first DSTROBE edge time (tDZFS) (modes higher than 4 only) . 219 B.5.2.14 First DSTROBE time (tFS) 220 B.5.2.15 Limited interlock time (tLI) 220 B.5.2.16 Limited interlock time with minimum (tMLI) . 221 B.5.2.17 Unlimited interlock time (tUI). 221 vi B.5.2.18 Maximum driver release time (tA
49、Z) . 221 B.5.2.19 Minimum delay time (tZAH) . 222 B.5.2.20 Minimum driver assert/negate time (tZAD) 223 B.5.2.21 Envelope time (tENV) . 223 B.5.2.22 STROBE to DMARDY- time (tSR) 224 B.5.2.23 DMARDY- to final STROBE time (tRFS) . 224 B.5.2.24 DMARDY- to pause time (tRP) 225 B.5.2.25 Maximum IORDY release time (tIORDYZ) . 226 B.5.2.26 Minimum IORDY assert time (tZIORDY) 226 B.5.2.27 Setup and hold before DMACK- time (tACK) . 227 B.5.2.28 STROBE to DMARQ/STOP time (tSS) . 227 B.5.2.29 Data setup time at IC component (tDSIC) (modes higher than 4 only) 227 B.5.2.30 Data
