1、ANSI/ESDA/JEDEC JS-002-2014 Revision and Replacement of ANSI/ESD S5.3.1-2009 315-339-6937; FAX: 315-339-6793; www.esda.org 2 JEDEC Global Standards for the Microelectronics Industry; www.jedec.org 3 IEC International Electrotechnical Commission, www.iec.ch ANSI/ESDA/JEDEC JS-002-2014 2 Charged devic
2、e model (CDM) electrostatic discharge (ESD) tester. Equipment (referred to as “tester“ in this standard) that simulates the device level CDM ESD event using the non-socketed test method. Dielectric layer. A thin insulator placed atop the Field Plate used to separate the device from the field plate.
3、Field plate. A conductive plate used to elevate the potential of the device under test (DUT) by capacitive coupling (see Figure 1). Ground plane. A conductive plate used to complete the circuitry for grounding / discharging the DUT (see Figure 1). Software voltage. A user/operator-entered voltage th
4、at, when combined with the scale factor or offset, sets the actual field plate voltage on the system in order to achieve the waveform parameters as defined in Tables 1 or 2. Test condition (TC). For purposes of this document, a test condition refers to the tester plate voltage that meets the wavefor
5、m parameter conditions in a particular column of Tables 1 and 2. 4.0 PERSONNEL SAFETY DURING INITIAL EQUIPMENT SETUP, A SAFETY ENGINEER OR APPLICABLE SAFETY REPRESENTATIVE SHALL INSPECT THE EQUIPMENT IN ITS OPERATING LOCATION TO ENSURE THAT THE EQUIPMENT IS NOT OPERATED IN A COMBUSTIBLE (HAZARDOUS)
6、ENVIRONMENT. 4.1 TRAINING ALL PERSONNEL SHALL RECEIVE SYSTEM OPERATIONAL TRAINING AND ELECTRICAL SAFETY TRAINING PRIOR TO USING THE EQUIPMENT. 4.2 PERSONNEL SAFETY THE PROCEDURES AND EQUIPMENT DESCRIBED IN THIS DOCUMENT MAY EXPOSE PERSONNEL TO HAZARDOUS ELECTRICAL CONDITIONS. USERS OF THIS DOCUMENT
7、ARE RESPONSIBLE FOR SELECTING EQUIPMENT THAT COMPLIES WITH APPLICABLE LAWS, REGULATORY CODES AND BOTH EXTERNAL AND INTERNAL POLICY. USERS ARE CAUTIONED THAT THIS DOCUMENT CANNOT REPLACE OR SUPERSEDE ANY REQUIREMENTS FOR PERSONNEL SAFETY. GROUND FAULT CIRCUIT INTERRUPTERS (GFCI) AND OTHER SAFETY PROT
8、ECTION SHOULD BE CONSIDERED WHEREVER PERSONNEL MIGHT COME INTO CONTACT WITH ELECTRICAL SOURCES. ELECTRICAL HAZARD REDUCTION PRACTICES SHOULD BE EXERCISED AND PROPER GROUNDING INSTRUCTIONS FOR EQUIPMENT SHALL BE FOLLOWED. NOTE: IN ADDITION, CDM TESTERS HAVE MOVING PARTS WHEN IN OPERATION AND CARE SHO
9、ULD BE TAKEN TO AVOID PERSONNEL CONTACT WITH MOVING PARTS WHEN IN OPERATION. 5.0 REQUIRED EQUIPMENT 5.1 CDM ESD Tester Figure 1 represents the hardware schematic for a CDM tester setup to conduct field-induced CDM ESD testing assuming the use of a resistive current probe. The DUT may be an actual de
10、vice or it may be one of the two verification modules (metal discs) described in Annex A. The pogo pin shall be connected to the ground plane with a 1 ohm current path with a minimum bandwidth (BW) of 9 gigahertz (GHz). The 1 ohm pogo pin to ground connection of the resistive current sensor may be a
11、 parallel combination of a 1 ohm resistor between the pogo pin and the ground plane and the 50 ohm impedance of the oscilloscope and its coaxial cable. K1 is the ANSI/ESDA/JEDEC JS-002-2014 3 switch between charging the field plate and grounding the field plate. The CDM ESD testers used within the c
12、ontext of this standard shall meet the waveform characteristics specified in Figure 2, and Tables 1 and 2, without additional passive or active devices, such as ferrites, in the probe assembly. Figure 1: Simplified CDM Tester Hardware Schematic NOTE: When constructing the test equipment, the parasit
13、ics in the charge and discharge paths should be minimized since the resistance inductance-capacitance (RLC) parasitics in the equipment greatly influence the test results. NOTE: For existing equipment designed to meet ANSI/ESD 5.3.1 and / or JEDEC C101 standards, it is recommended to contact qualifi
14、ed service personnel to determine compliance to this standard upon removal of ferrite components. 5.1.1 Current Sensing Element A current sensing element shall be incorporated into the ground plane. The resistance of this element shall have a value of 1.0 ohm + 10%. A resistor, as specified in Secti
15、on 5.1, shall be used as the current sensing element. The value of resistance (including the 50 ohm cable / oscilloscope termination) shall be measured using an ohmmeter as described in Section 5.5. The resistance value shall be used to calculate the first peak current. The current sensing element s
16、hall have a minimum frequency response of 9 GHz (specified by maximum rolloff of 3 dB at 9 GHz). 5.1.2 Ground plane The probe assembly shall contain a square ground plane with the probe pin centered within it as shown in Figure 1. The dimensions of the ground plane shall be 63.5 mm x 63.5 mm + 6.35
17、mm (2.5 inches x 2.5 inches + 0.25 inches). 5.1.3 Field Plate / Field Plate Dielectric Layer The field plate shall have a surface flatness to vary no more than + 0.127 mm (0.005 inch). The field plate dielectric layer should be made with a FR4 or similar epoxy-glass material. For FR4, the thickness
18、and thickness tolerance of this dielectric layer should be 0.381 mm + 0.0254 mm (0.015 inches + 0.001 inches) in order to result in a capacitance measurement (as specified in normative Annex B) in the range specified in Table 4 in Annex A. If a different material is used, the material thickness is c
19、hosen to result in a capacitance measurement in the range specified in Table 4 in Annex A. Pogo pin to ground resistance = 1 002.1.2014 ANSI/ESDA/JEDEC JS-002-2014 4 5.1.4 Charging Resistor The charging resistor shown in Figure 1 shall nominally be 100 megohms or greater. Resistor values higher than
20、 100 megohms may be used, but this may not allow very large devices (refer to Section 6.9 and Annex H) to charge fully before being discharged by the probe assembly. This effect can be overcome by adding a delay between discharges in the CDM tester programming software. If using a resistor greater t
21、han 100 megohms, it is recommended that the tester or the device itself be characterized to determine if a delay is needed for discharging large devices. A procedure for this large device delay characterization is given in Annex H. 5.2 Waveform Measurement Equipment The CDM waveform measurement equi
22、pment shall consist of the following components. 5.2.1 Cable Assemblies Cable assemblies with combined internal tester cable and external cable total loss of no more than 2 dB at frequencies up to 9 GHz and a nominal 50 ohm impedance. 5.2.2 Equipment for High Bandwidth Waveform Measurement 5.2.2.1 H
23、igh Bandwidth Oscilloscope An oscilloscope or transient digitizer with a minimum real-time (single shot) 3 dB BW of at least 6 GHz and 20 gigasample/sec sampling rate with a nominal 50 ohm input impedance. 5.2.2.2 Attenuator A 20 dB attenuator with a precision of 0.5 dB, at least 12 GHz BW, and an i
24、mpedance of 50 ohms 5.0 ohms. 5.2.3 Equipment for 1.0 GHz Waveform Measurement 5.2.3.1 1 GHz Oscilloscope An oscilloscope or transient digitizer with a real-time (single shot) 3 dB BW of 1 GHz with a nominal 50 ohm input impedance. The sampling rate shall be 5 gigasample/sec. NOTE: The user has an o
25、ption of using a higher BW oscilloscope and using a hardware or software filter to produce a bandwidth and sampling rate equivalent to that specified in Section 5.2.3.1. 5.2.3.2 Attenuator A 20 dB attenuator with a precision of 0.5 dB, at least 4 GHz BW, and an impedance of 50 ohms 5 ohms. 5.3 Verif
26、ication Modules (Metal Discs) The large verification module shall have a capacitance of 55 pF 5% and the small verification module shall have a capacitance of 6.8 pF 5%. Refer to normative Annex A for information on the verification module physical dimensions and normative Annex B for information on
27、 the capacitance measurement procedure. 5.4 Capacitance Meter Capacitance meter with a resolution of 0.2 pF, a measurement accuracy of 3%, and a measurement frequency of 1.0 MHz as described in normative Annex B. ANSI/ESDA/JEDEC JS-002-2014 5 5.5 Ohmmeter The ohmmeter used to measure the resistance
28、of the resistive probe shall be capable of measuring to an accuracy of 0.01 ohm. Use of Kelvin 4-wire connections is recommended. 6.0 PERIODIC TESTER QUALIFICATION, WAVEFORM RECORDS, AND WAVEFORM VERIFICATION REQUIREMENTS 6.1 Overview of Required CDM Tester Evaluations 6.1.1 The CDM tester shall be
29、qualified, re-qualified, and periodically verified as described in this section. The safety precautions described in Section 4 shall be followed at all times. NOTE: Dielectric layers, ground planes (ground plates), the coaxial discharging resistor (probe), the distance between the ground plane and t
30、he field plate, the verification modules and the discharge contacts (e.g., pogo pins) are key elements of the tester construction. Any change to these elements requires a waveform verification. NOTE: Changes in the shape of the discharge pulse, even though they may still be within specification, may
31、 indicate degradation of the discharge path. 6.2 Waveform Capture Hardware 6.2.1 Waveform capture requires the following instrumentation and tester set voltage procedure: Oscilloscope - as specified in Section 5.2. Attenuator and cable assembly as defined in Section 5.2. Verification modules (as des
32、cribed in Section 5.3) - with the dimensions and attributes listed in normative Annex A and method of measurement listed in Normative Annex B. 6.3 Waveform Capture Setup 6.3.1 Clean the verification modules. Avoid skin contact with the modules prior to, and during testing. A recommended procedure is
33、 described in normative Annex A. 6.3.2 Using an alcohol wipe, clean the discharge probe and the field charge plate on which the device is placed to remove any surface contamination that could result in charge loss. Ensure the pogo pin is free of particulates. 6.3.3 Attach the appropriate 20 dB atten
34、uator as described in Section 5.2 to the oscilloscope. Attach one end of the external cable assembly, as described in Section 5.2.1, to the attenuator and the other end to the CDM tester. Verify all connections in the measurement chain are tight. See informative Annex E for an example of oscilloscop
35、e settings and captured waveforms. 6.4 Waveform Capture Procedure 6.4.1 Place the verification module to be used on the field plate dielectric, ensuring intimate contact between the field plate dielectric and verification module. 6.4.2 Set the potential of the field plate to the needed voltage for t
36、he test condition being run. 6.4.3 Align the ground pin to approximately the center of the verification module. ANSI/ESDA/JEDEC JS-002-2014 6 6.4.4 Either the single discharge or dual discharge method as described in Annex F.1 or F.2 respectively can be used, but the discharge method chosen should b
37、e consistent with how product will be tested. When using the dual discharge method, waveforms for positive and negative pulses require a change in the oscilloscope trigger conditions to capture only positive or negative pulses. 6.4.5 Discharge the verification module at least ten times at the polari
38、ty being verified. 6.4.6 Observe at least ten successive waveforms during the set of discharges above and record the average waveform parameters for Ip, Tr, full width at half maximum (FWHM), and Ip2 for this group of waveforms as shown in Figure 2. 6.4.7 If the waveform characteristics do not meet
39、the requirements as defined in either Tables 1 or 2 for the target test condition (See Sections 6.5 and 6.6 for the appropriate table and test conditions to use), re-clean the verification modules and ground pin, check that all connections are tight, make adjustments in the field plate voltage and r
40、epeat steps 6.4.1 through 6.4.7. NOTE: If this still does not work, check the system vacuum or look at replacement of the ground pin. Consult the tester manufacturer for more information. 6.4.8 Repeat the procedure for the opposite polarity. 6.5 CDM Tester Qualification/Re-Qualification Procedure 6.
41、5.1 CDM Tester Qualification/Re-Qualification Procedure The intent of the qualification / requalification procedure is to determine the field plate voltage needed for each test condition setting (125 1000) in Table 3 to produce peak current in the ranges corresponding to Tables 1 and 2, and therefor
42、e corresponding to the classification levels as specified in Table 3. Two alternative procedures for how to qualify and routinely check the CDM test system are introduced in Annex G. These procedures are based on generally available CDM test systems and offer two methods for adjusting the field plat
43、e voltage to meet the waveform parameters of Tables 1 or 2. CDM test system manufacturers, or test system operators, may develop alternate qualification procedures from the two procedures in Annex G, as long as they result in waveforms which meet the requirements of Tables 1 or 2 for the various tes
44、t conditions. It is recommended that settings determined from this qualification procedure be recorded for a particular test system, oscilloscope BW and polarity. This allows for detection of drift over time on the system, which may indicate a larger issue with the system. See Section G.3 for exampl
45、es. 6.5.1.1 Perform the setup and waveform capture steps as described in Sections 6.3 and 6.4 under Test Conditions 125-1000 in Table 2 for both positive and negative polarities using both small and large verification modules and measuring with the high bandwidth oscilloscope as specified in Section
46、 5.2.2.1. Refer to Annex G for example flowcharts of the procedures. NOTE: If local site test voltage ranges will always be narrower than the range above (for example Test Conditions 125-500), it is permissible to perform the qualification within that narrower range. ANSI/ESDA/JEDEC JS-002-2014 7 6.
47、5.2 Conditions Requiring CDM Tester Qualification / Re-qualification 6.5.2.1 CDM tester qualification and re-qualification as described in this section is required in the following situations: Acceptance testing when the CDM tester is delivered; usually performed by the manufacturer during installat
48、ion. Periodic re-qualification in accordance with manufacturers recommendations. The maximum time between re-qualification tests is one year. After service or repair that could affect the waveform. 6.5.3 1 GHz Oscilloscope Correlation with High Bandwidth Oscilloscope 6.5.3.1 During first acceptance
49、testing, the tester manufacturer shall use a high bandwidth oscilloscope as specified in Section 5.2.2.1 for initial waveform capture. If the test site only has a 1 GHz oscilloscope as specified in Section 5.2.3.1, the tester manufacturer and end user shall confirm using appropriate bandwidth filtering techniques and comparison with the oscilloscope from the tester manufacturer that the users oscilloscope measures tester waveforms as defined in Table 1 for quarterly and routine waveform acceptance. NOTE: The Bessel-Thomson software filter option on many osci
