1、 For Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level Electrostatic Discharge Association 7900 Turin Rd., Bldg. 3 Rome, NY 13440 An American National Standard Approved February 27, 2018 ANSI/ESD SP5.4.1-2017 ESD Association Standard Practice for
2、 Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level Approved September 20, 2017 EOS/ESD Association, Inc. ANSI/ESD SP5.4.1-2017 Electrostatic Discharge Association (ESDA) standards and publications are designed to serve the public interest by elim
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12、TIES. Published by: EOS/ESD Association, Inc. 7900 Turin Road, Bldg. 3 Rome, NY 13440 Copyright 2018 by ESD Association All rights reserved No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher
13、. Printed in the United States of America ISBN: 1-58537-296-XCAUTION NOTICE DISCLAIMER OF WARRANTIES DISCLAIMER OF GUARANTY LIMITATION ON ESDAs LIABILITY ANSI/ESD SP5.4.1-2017 i (This foreword is not part of ESD Association Standard Practice ANSI/ESD SP5.4.1-2017) FOREWORD Latch-up failures can occu
14、r in products which do not show latch-up sensitivity when tested with “static” pulses (JEDEC JESD78E). The trigger for latch-up in these situations is often found to be very fast transients, either on input or output circuits or power supplies. This kind of latch-up is called transient induced latch
15、-up, commonly known as transient latch-up (TLU). Such fast transients might be, but are not limited to, electrostatic discharges like ESD system level pulses or cable discharge events. TLU is a real threat for integrated circuits. In technical report TR5.4-04-13 (published July 2013) written by ESDA
16、 WG 5.4, several examples of TLU are listed. Those examples can be categorized with respect to the occurrence and the root cause of the TLU and with respect to appropriate test methods to reproduce the TLU event in a lab. There are several examples published in which ICs are latch-up sensitive in st
17、ress tests which are intended to reproduce real-world stress conditions and therefore there is a certain risk that TLU can occur in the field. There are even examples of field returns which have to be avoided by all means. Therefore, a characterization methodology to guarantee a certain robustness o
18、f potentially susceptible pins of ICs in the application is desirable. The “static” standard latch-up qualification procedure JEDEC JESD78E currently does not cover transient threats. The former TLU standard practice1, ANSI/ESD SP5.4 (now ESD TR5.4-03-11), is difficult to relate to real world stress
19、. Lacking any appropriate standard, test equipment which could reproduce typical field fails is currently not available commercially. Currently TLU studies must be done using experimental prototypes which address some of the known TLU examples. The TLU test method requires a pre-conditioning of the
20、device, a stress pulse to the device and a latch-up detection mechanism. These steps are similar to the procedure in ESD TR5.4-03-11, however, with different constraints to the blocks which allows a more universal approach to todays applications. This document defines pre-conditioning of the device-
21、under-test, applying the stress pulse, detecting latch-up, and determining failure criteria with a special focus on the verification of all components of the TLU set-up. The procedures described in the standard practice shall be used as a method to characterize possible susceptible pins of a device.
22、 It is not the intention of the working group that this method be used as a “standard qualification methodology” of a product, as, for example, the static latch-up qualification according to JEDEC JESD78E. This document was designated ANSI/ESD SP5.4.1-2017 and approved on September 20, 2017. 1 ESD A
23、ssociation Standard Practice (SP): A procedure for performing one or more operations or functions that may or may not yield a test result. Note, if a test result is obtained it is not reproducible. ANSI/ESD SP5.4.1-2017 ii At the time ANSI/ESD SP5.4.1-2017 was prepared, the 5.4 Device Testing (TLU)
24、Subcommittee had the following members: Wolfgang Stadler, Chair Intel Deutschland GmbH Robert Ashton ON Semiconductor (Retired) Jon Barth Barth Electronics, Inc. Brett Carn, TAS Rep Intel Corporation Lorenzo Cerati STMicroelectronics Marcel Dekker MASER Engineering Reinhold Gaertner Infineon Technol
25、ogies AG Horst Gieser Fraunhofer EMFT Vaughn P. Gross Green Mountain ESD Labs, LLC Evan Grund Grund Technical Solutions, Inc. Leo G. Henry ESD/TLP Consultants Timothy J. Maloney CAI Tom Meuse Thermo Fisher Scientific Gregory OSullivan Micron Semiconductor, Inc. Nathaniel Peachey Qorvo, Inc. Bill Rey
26、nolds GLOBALFOUNDRIES Alan Righter Analog Devices, Inc. Masanori Sawada Hanwa Electronic Ind. Co, Ltd. Mirko Scholz imec Theo Smedes NXP Semiconductors Dietmar Walther Texas Instruments, Inc. Terry Welsher Dangelmayer Associates Xiong Ying Huawei The following individuals made significant contributi
27、ons to ANSI/ESD SP5.4.1-2017: Krzysztof Domanski Intel Deutschland GmbH Steven Voldman Steven H. Voldman, LLC Scott Ward Texas Instruments, Inc. ANSI/ESD SP5.4.1-2017 iii TABLE OF CONTENTS 1.0 PURPOSE, SCOPE, AND APPLICATION . 1 1.1 PURPOSE . 1 1.2 SCOPE . 1 1.3 APPLICATION 1 2.0 REFERENCED DOCUMENT
28、S . 1 3.0 DEFINITION OF TERMS . 2 4.0 PERSONNEL SAFETY . 2 5.0 DEVICE HANDLING . 3 6.0 GENERAL TLU CHARACTERIZATION FLOW . 3 7.0 EQUIPMENT AND VERIFICATION 4 7.1 SCHEMATIC OF THE TLU CHARACTERIZATION SET-UP 4 7.1.1 Set-up for Overvoltage TLU Test of a Supply Pin (Supply Test) . 4 7.1.2 Set-up for TL
29、U Injection to IO Pin (I Test): 5 7.1.3 Set-up for TLU Injection to Signal Pin (Test of Signaling Latch-up) 6 7.2 TLU PULSE SOURCE 6 7.2.1 General Considerations . 6 7.2.2 Recommended Standard Pulses . 7 7.2.3 Verification Scheme . 9 7.3 POWER SUPPLY . 9 7.3.1 General Considerations . 9 7.3.2 Power
30、Supply Verification Scheme 10 7.4 GENERAL TEST EQUIPMENT 11 7.4.1 Oscilloscope . 11 7.4.2 Current Sensor . 11 7.4.3 Voltage Probes . 11 7.4.4 Decoupling Device . 11 8.0 TLU CHARACTERIZATION . 11 8.1 GENERAL CONSIDERATIONS 11 8.2 PRE-CONDITIONING 11 8.3 PRE-STRESS CURRENT CONSUMPTION READ-OUT . 12 8.
31、4 APPLYING LATCH-UP STRESS 12 8.5 DETECTING LATCH-UP 13 8.5.1 Detecting Latch-up at Supply Due to Supply Overstress or IO Injection . 13 ANSI/ESD SP5.4.1-2017 iv 8.5.2 Detecting Signaling Latch-up at Signal Pins Due to Supply Overstress or Current Injection 13 8.6 POST-STRESS READ-OUT AFTER TLU STRE
32、SS 13 ANNEXES Annex A (Informative) Bibliography 14 Annex B (Informative) List of Pins Particularly Susceptible to TLU 15 Annex C (Informative) Examples for Components for TLU Set-ups . 16 Annex D (Informative) Examples for Components for Power Supply Verification Set-ups. 17 Annex E (Informative) R
33、evision History for ANSI/ESD SP5.4.1-2017 20 FIGURES Figure 1: General TLU Test Flow . 3 Figure 2: Basic Set-up for the Overvoltage Test of VDD Supply . 5 Figure 3: Basic Set-up for the Current Injection Test to a Signal Pin . 6 Figure 4: Pulse Parameters of the TLU Square Pulse . 9 Figure 5: Circui
34、t for Testing Power Supply Response 10 Figure 6: Simple Experimental TLU Set-up 16 Figure 7: Schematic of Circuit for Characterization of Power Supply Response . 17 Figure 8: Drain to Source versus Gate to Source Voltage for the NTTFS4C25N 18 Figure 9: Gate to Source Voltage versus Total Gate Charge
35、 for the NTTFS4C25N . 19 TABLES Table 1: Parameters of Standard TLU Square Pulses . 8ESD Association Standard Practice ANSI/ESD SP5.4.1-2017 1 ESD Association Standard Practice for Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits - Transient Latch-up Testing - Device Level 1.0 PURPOSE
36、, SCOPE, AND APPLICATION 1.1 Purpose This document addresses steps which are required to perform transient latch-up (TLU) characterization under well-defined conditions. It defines pre-conditioning of the device-under-test (DUT), applying the stress pulse, detecting latch-up, and determining failure
37、 criteria. Additionally, a procedure to verify the test equipment is described. The test methods enable the user to perform an application specific TLU characterization with reliable and verified test set-ups. 1.2 Scope This document defines procedures to characterize the latch-up sensitivity of int
38、egrated circuits triggered by fast transients. 1.3 Application This document defines a characterization methodology which is intentionally kept as flexible as possible. This document does not define a qualification standard. The characterization can be applied to: Test structures (for example, proce
39、ss assessment, component verification). Distinct pins of products (stand-alone and with “simple” external circuitries). I/O pins of systems and subsystems. Integrated circuits with or without external circuitry which is typical for the application or required for pre-conditioning the IC. The IC migh
40、t be mounted on a printed-circuit board (PCB). In order to perform the TLU test one has to define the pins under test and the testing parameters. This document is intended to be a guideline for the application engineer who defines the test and the test engineer who performs the test according to the
41、 definition and prepares a report. The characterization is application specific. Hence, the focus of this document is on the general methodology and particularly on verification of the methodology. TLU as defined in this document does not cover changes of functional states, even if those changes wou
42、ld result in a low-impedance path and increased power supply consumption. 2.0 REFERENCED DOCUMENTS Unless otherwise specified, the latest issue, revision or amendment of the following documents form a part of this standard to the extent specified herein: ESD ADV1.0, ESD Association Glossary of Terms
43、2 ANSI/ESD S20.20, Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices)2 ANSI/ESD STM5.5.1, For Electrostatic Discharge Sensitivity Testing Transmission Line Pulse (TLP) Component Level2 IEC61340-5-1, ElectrostaticsPart 5-1: Pro
44、tection of Electronic Devices from Electrostatic PhenomenaGeneral Requirements3 2 EOS/ESD Association, Inc. 7900 Turin Road, Bldg. 3, Rome, NY 13440, Ph: 315-339-6937; www.esda.org 3 IEC International Electrotechnical Commission, www.iec.ch ANSI/ESD SP5.4.1-2017 2 JESD78E “IC Latch-up Test”, JEDEC,
45、April 20164 NOTE: For the use in this document, the version JESD78E is required. JESD625, Requirements for Handling Electrostatic Discharge-Sensitive (ESDS) Devices4 3.0 DEFINITION OF TERMS The following definitions are in addition to those found in ESD ADV 1.0, ESD Associations Glossary of Terms: f
46、unctional state. The mode in which the device is operating. NOTE: A device may have many different functional states each resulting in a different supply current. ground pin. The common or zero-potential pin(s) of the DUT. NOTE: These pins are generally biased to 0 volts and all measurements are mad
47、e relative to this reference. maximum operating voltage (maximum Vsupply). Value listed in the device data sheets for which the device will still meet all specifications under operating conditions. It is not the same as the absolute maximum voltage allowed without causing permanent damage. maximum s
48、tress voltage (MSV). The maximum voltage allowed to be applied to the stressed pin during TLU testing without causing catastrophic damage to the device. NOTE: MSV might depend on the TLU stress pulse width; it can be larger than the absolute maximum rated voltage. nominal supply current (Inom). The
49、measured DC supply current for each VDD supply. The nominal supply current is in the range of supply currents possible under all normal operating states. preconditioning. The process of setting the input states of a device and applying appropriate electrical signals until a particular desired functional state is achieved. signal pins. Any connected pin that does not supply power or ground to the component. signaling (transient) latch-up. Latch-up phenomenon which occurs between any signal pin (input, output, I/O) and any other pin; for example, neighboring
