1、Designation: E431 96 (Reapproved 2011)Standard Guide toInterpretation of Radiographs of Semiconductors andRelated Devices1This standard is issued under the fixed designation E431; the number immediately following the designation indicates the year oforiginal adoption or, in the case of revision, the
2、 year of last revision. A number in parentheses indicates the year of last reapproval. Asuperscript epsilon () indicates an editorial change since the last revision or reapproval.1. Scope1.1 This guide provides illustrations of radiographs ofsemiconductors and related devices. Low powered transistor
3、s(through the TO-11 case configuration), diodes, low-powerrectifiers, power devices, and integrated circuits are illustratedwith common assembly features. Particular areas of construc-tion are featured for these devices detailing critical points ofdesign or assembly.1.2 This standard does not purpor
4、t to address all of thesafety concerns, if any, associated with its use. It is theresponsibility of the user of this standard to establish appro-priate safety and health practices and determine the applica-bility of regulatory limitations prior to use.2. Referenced Documents2.1 ASTM Standards:2E801
5、Practice for Controlling Quality of Radiological Ex-amination of Electronic DevicesE1161 Practice for Radiologic Examination of Semiconduc-tors and Electronic ComponentsE1255 Practice for RadioscopyE1316 Terminology for Nondestructive Examinations3. Terminology3.1 Definitions of terms used in these
6、reference illustrationsmay be found in Terminology E1316, Section D.4. Significance and Use4.1 Illustrations provided in this guide are intended for useas references to aid in interpreting film or nonfilm imagesresulting from x-ray examinations (see Table 1) to ascertainquality of assembly and workm
7、anship.4.2 Required attributes of the design features or otherconstruction details are not provided but are to be establishedas mutually agreed upon by manufacturers and users of thesedevices. Many devices share common assembly features; thus,these interpretations can be used for components not illu
8、s-trated.5. Use of Illustrations5.1 The illustrations in this guide are for use in interpretingradiographs of semiconductors and related devices. Theyprovide reference points and information on the critical areasof such devices. These points must be clearly resolved in theradiographs being interpret
9、ed. The radiographs to be inter-preted must comply with the requirements of Practice E801 toensure suitable image quality with minimal distortion. Addi-tional information on the application of radiographic tech-niques to semiconductors and electronic components may befound in Test Method E1161.5.2 T
10、he illustrations in this guide may also be used tointerpret the radioscopic images of semiconductors and relateddevices when using radioscopic techniques. The radioscopicimages to be interpreted must comply with the requirements ofPractice E801 to ensure suitable image quality with minimaldistortion
11、. Additional information on the application of radio-scopic techniques may be found in Test Method E1161 andPractice E1255.6. Description6.1 Description of irregularities and applicable figures areshown in Table 1.7. Keywords7.1 electronic devices; nondestructive testing; radiographs;radiography; re
12、ference illustrations; semiconductors; x-ray1This guide is under the jurisdiction of ASTM Committee E07 on Nondestruc-tive Testing and is the direct responsibility of Subcommittee E07.02 on ReferenceRadiological Images.Current edition approved Dec. 1, 2011. Published March 2012. Originallyapproved i
13、n 1971. Last previous edition approved in 2007 as E431 - 96(2007). DOI:10.1520/E0431-96R11.2For referenced ASTM standards, visit the ASTM website, www.astm.org, orcontact ASTM Customer Service at serviceastm.org. For Annual Book of ASTMStandards volume information, refer to the standards Document Su
14、mmary page onthe ASTM website.1Copyright ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959, United States.TABLE 1 Irregularity Description and Figure ReferencesItem and Irregularity Expressed asFigureReferenceTransistors, low-power (TO-11 and smaller packages)E
15、xtraneous matter Any material contained in the semiconductor device that is not necessary for its manufacture oroperation.1Internal lead irregularities, bond-to-post connection Leads extending beyond attachment points at either end. Allowable extension should be stated inwire diameters.2(a)Slack lea
16、ds deviate from a straight line between attachment points. Allowable deviation shouldbe stated in wire diameters.2(b)Internal lead clearance is the distance between the edge of the chip and lead wire. Allowableclearance should be stated in wire diameters.2(c)Post-position irregularities Allowable de
17、viations of the post from its intended (design) position may be specified as minimumangle made by the post and header, or as clearance between post and post or post and caseexpressed in terms of post diameter.3Getter-position irregularities In crimp-type devices, deviations of the getter ring from i
18、ts intended (design) position are statedrelative to the crimp. In noncrimp-type devices, deviations of the getter ring from its intended(design) position are stated as the angle between the actual and intended positions.4(a)4(b)Mounting paste Mounting-paste buildup or expulsion, or both, is an exces
19、sive amount of material used to mountthe semiconductor element on the header. Allowable excess should be measured relative tothe surfaces, clearances, and shape of the deposit.5Post-connection solder or gold paste Post-connection solder or gold-paste buildup is an excessive amount of such material a
20、t thetermination. Excess is measured relative to the diameter at the attachment point and by thedeposit shape.6Diodes and low-power rectifiers (whisker-type)Extraneous matter Any material contained in the cavity of the device that is not part of its design and not requiredfor its manufacture or oper
21、ation.7(a)7(b)7(c)Whisker irregularities Any whisker malformation from its intended shape caused by compression. Allowablecompression is stated as a percentage of design length.8(a)Whisker cross-sectionalarea deviations are stated as a percentage of cross section. 8(b)Misalignment irregularities are
22、 described by device design and type of construction. noneWhisker contact to the post or lead is expressed as a percentage of the design contact area. 8(c)Crimped lead devices Minimum crimp length can be stated. 9Crystal and crystal-mounting irregularities Tilt is the deviation of the mounted crysta
23、l from its intended (design) mounting plane. Allowabledeviation is expressed in degrees from normal to the main axis of the device.10(a)Clearance is the distance from the edge of the crystal to the inside wall of the device cavity. It isexpressed in units of length (millimetres or inches); if contac
24、t is permissible, it should be statedwhether or not fusion is allowable.10(b)10(c)Crystal fusion to the mount is an area of contact between the crystal and the designed mountingsurface where fusion occurs. Minimum allowable fusion is stated as a percentage of the designmounting surface.10(d)Mounting
25、-paste expulsion is excessive mounting paste. Allowable expulsion is stated as depositshape.10(e)Diodes and low-power rectifiers (whiskerless-type)Misalignment Crystal position relative to the posts or the posts to one another or both. Allowable crystalmisalignment is stated as a percentage of the l
26、argest post. Allowable post misalignment isexpressed as a percentage of the diameter of the smallest post.11(a)11(b)Voids Air bubbles in the encapsulation material used for the semiconductor device. Allowable voids arestated as a percentage of wall thickness and as the distance from the encapsulatio
27、n ends tothe lead seal.12Integrated circuitsExtraneous matter Any material contained in the integrated circuit that is not part of its design and not necessary forits manufacture or operation.noneClearances Minimum allowable clearances are expressed in units of length (millimetres or inches) or lead
28、-wire diameters. Internal clearances can be stated between parts as: (1) lead to case; (2) leadwire to lead wire; (3) lead wire to bond; (4) lead wire to chip; (5) chip to chip; (6) bond to bond;(7) lead wire to external lead.13Chip mounting The minimum area of mounting paste used to secure the chip
29、 to the header is stated as apercentage of the design contact (chip) area.14(a)Unacceptable configuration of voids should be described. 14(b)A misaligned chip is one misoriented with respect to its intended position. Misalignment isexpressed as an angle or a case-to-chip distance.noneMounting-paste
30、buildup or expulsion (or both) An excessive amount of the material used to mount the semiconductor element to the header.Allowable excess is measured relative to the top surface of the semiconductor element and bydeposit shape.5Internal lead irregularities, bond-to-external lead, andbond-to-bond or
31、bond-to-bond leadsLeads extending beyond the attachment points at either end. Allowable extension is stated inwire diameters.noneSlack leads deviate from a straight line between the attachment points. Allowable deviation isexpressed in wire diameters.noneE431 96 (2011)2TABLE 1 ContinuedItem and Irre
32、gularity Expressed asFigureReferencePower devices (transistors, rectifiers, and silicon-controlled rectifiers)Construction methods and designs Because of the large variety of construction methods and designs, it will generally be necessaryto state criteria for each type of device. The usual criteria
33、 should include examinations for: (1)extraneous matter; (2) internal clearances; (3) mounting-paste buildup and expulsion; (4) crimpirregularities, where internal leads are crimped into tubular, external leads; (5) internal-connection irregularities.noneFIG. 1 TransistorExtraneous Matter(a) Bond-to-
34、Post Connection (b) Slack Leads(c) Internal Lead ClearanceFIG. 2 TransistorInternal Lead IrregularitiesFIG. 3 TransistorPost-Position IrregularitiesE431 96 (2011)3FIG. 4 TransistorGetter Position IrregularitiesFIG. 5 TransistorMounting Paste Buildup or Expulsion or BothFIG. 6 TransistorPost-Connecti
35、on Solder or Paste BuildupE431 96 (2011)4FIG. 7 Diodes, Low-Power Rectifiers (Whisker-Type)ExtraneousMatterE431 96 (2011)5FIG. 8 Diodes, Low-Power Rectifiers (Whisker-Type)WhiskerIrregularitiesFIG. 9 Diodes, Low-Power Rectifiers (Crimped Lead Devices)FIG. 10 Diodes, Low-Power Rectifiers (Whisker-Typ
36、e)Crystaland Crystal Mounting IrregularitiesFIG. 11 Diodes and Low-Power Rectifiers (Whiskerless-Type)MisalignmentE431 96 (2011)6ASTM International takes no position respecting the validity of any patent rights asserted in connection with any item mentionedin this standard. Users of this standard ar
37、e expressly advised that determination of the validity of any such patent rights, and the riskof infringement of such rights, are entirely their own responsibility.This standard is subject to revision at any time by the responsible technical committee and must be reviewed every five years andif not
38、revised, either reapproved or withdrawn. Your comments are invited either for revision of this standard or for additional standardsand should be addressed to ASTM International Headquarters. Your comments will receive careful consideration at a meeting of theresponsible technical committee, which yo
39、u may attend. If you feel that your comments have not received a fair hearing you shouldmake your views known to the ASTM Committee on Standards, at the address shown below.This standard is copyrighted by ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959,United
40、 States. Individual reprints (single or multiple copies) of this standard may be obtained by contacting ASTM at the aboveaddress or at 610-832-9585 (phone), 610-832-9555 (fax), or serviceastm.org (e-mail); or through the ASTM website(www.astm.org). Permission rights to photocopy the standard may also be secured from the ASTM website (www.astm.org/COPYRIGHT/).FIG. 12 Diodes and Low-Power Rectifiers (Whiskerless-Type)VoidsFIG. 13 Integrated CircuitsInternal ClearancesFIG. 14 Integrated CircuitsChip MountingE431 96 (2011)7
