1、BRITISH STANDARD BS6475:1984 Specification for Processor system bus interface (Eurobus A) UDC681.325:681.3182.7BS6475:1984 This BritishStandard, having been prepared under the directionof the Office and Information Standards Committee, was published underthe authority of the BoardofBSI and comesinto
2、effecton 30April1984 BSI02-2000 The following BSI references relate to the work on this standard: Committee reference OIS/13 Draft for comment83/61491DC ISBN 0 580 13789 9 Committees responsible for this BritishStandard The preparation of this BritishStandard was entrusted by the Office and Informat
3、ion Standards Committee (OIS/-) to Technical Committee OIS/13 upon which the following bodies were represented: British Gas Corporation British Railways Board British Telecommunications Business Equipment Trade Association Central Computer and Telecommunications Agency Department of Trade and Indust
4、ry (National Physical Laboratory) Electricity Supply Industry in England and Wales Electronic Engineering Association Institute of Measurement and Control Ministry of Defence Coopted member Amendments issued since publication Amd. No. Date of issue CommentsBS6475:1984 BSI 02-2000 i Contents Page Com
5、mittees responsible Inside front cover Foreword iv 0 Introduction 1 1 Scope 3 2 Definitions 3 3 Designation of a particular Eurobus 5 4 Compliance 5 5 Protocols for Eurobus A 5 6 Electrical and timing requirements 15 Appendix A Eurobus10/A logical implementation 25 Appendix B Eurobus18/A logical imp
6、lementation 25 Appendix C Eurobus26/A logical implementation 26 Appendix D Eurobus34/A logical implementation 26 Appendix E Connector allocation 27 Appendix F Examples of application of protocol rules 33 Appendix G Method of address allocation for mixed data widths 50 Appendix H Example of Eurobus b
7、ackplane construction 54 Appendix J Mechanical option1: forced air convection cooled double Eurocard for UK Ministry of Defence use with Eurobus18/A 54 Appendix K Extender panel 60 Appendix L Examples of the application of Eurobus A timing requirements 60 Appendix M Bus receiver a.c. noise rejection
8、 67 Appendix N Test circuit and waveform for determination of transient sink current 68 Figure 1 Eurobus with some typical devices 2 Figure 2 Bus terminations 16 Figure 3 End terminator/spur card 19 Figure 4 Test circuit 20 Figure 5 Signal edge characteristics 22 Figure 6 Allocation of an idle bus a
9、nd allocation of a bus already in use for a basic Read, Write or Vector cycle 33 Figure 7 Reallocation of a bus being used for a Hold or Retain cycle 36 Figure 8 Interrupt cycle 38 Figure 9 Read cycle 39 Figure 10 Write cycle 40 Figure 11 Vector cycle 41 Figure 12 Cycle time-out using cycle abort 43
10、 Figure 13 Memory protect using cycle abort 44 Figure 14 Multiple buses 46 Figure 15 Resolution of deadly embrace 47 Figure 16 Slave asks arbiter to remove allocation from master 49 Figure 17 Backplane cross section 54 Figure 18 MOD standard forced air convection cooled double Eurocard for Eurobus 1
11、8/A 56 Figure 19 Side1 (component side) 61BS6475:1984 ii BSI 02-2000 Page Figure 20 Side2 (non-component side) 62 Figure 21 Test pulses 67 Figure 22 Test circuit for determination of bus receiver a.c. noise rejection 68 Figure 23 Test circuit for determination of transient sink current 68 Figure 24
12、Test waveform for determination of transient sink current 69 Table 1 Eurobus A protocol lines 7 Table 2 Coding of byte mode/address space selection lines 9 Table 3 Address recognition protocol (N =7) 9 Table 4 Address modifier codes to be recognized by slave devices of different widths sharing the s
13、ame bus 10 Table 5 Identification of symbols 17 Table 6 Termination network resistor ratings 17 Table 7 Termination network diode characteristics 17 Table 8 Power supply ranges at the bus transmitters and receivers 18 Table 9 D.C. characteristics of the bus transmitter/receiver pair 19 Table 10 D.C.
14、 characteristics of the bus receiver 19 Table 11 D.C. characteristics of the bus transmitter 20 Table 12 A.C. noise rejection of the bus receiver 20 Table 13 A.C. requirements of the bus transmitter 20 Table 14 Current drawn from a bus line in the quiescent state 21 Table 15 Current output to a bus
15、line in the active state 21 Table 16 Properties of waveform 21 Table 17 Eurobus A timing 22 Table 18 Eurobus10/A byte address code 25 Table 19 Eurobus18/A byte address code 25 Table 20 Eurobus26/A byte address code 26 Table 21 Eurobus34/A byte address code 26 Table 22 Eurobus10/A allocation of conne
16、ctor pins to signals 27 Table 23 Eurobus18/A allocation of connector pins to signals 28 Table 24 Example of Eurobus18/A signal allocations in an actual implementation 29 Table 25 Eurobus26/A allocation of connector pins to signals 30 Table 26 Eurobus34/A allocation of connector B pins to signals 31
17、Table 27 Eurobus34/A allocation of connector A pins to signals 32 Table 28 Allocation of an idle bus 34 Table 29 Reallocation of a bus being used for a basic cycle 35 Table 30 Reallocation of a bus being used for a Hold or Retain cycle 37 Table 31 Interrupt cycle 39 Table 32 Read cycle 40 Table 33 W
18、rite cycle 41 Table 34 Vector cycle 42 Table 35 Cycle time-out using cycle abort 43 Table 36 Memory protect using cycle abort 45 Table 37 Resolution of deadly embrace 48BS6475:1984 BSI 02-2000 iii Page Table 38 Slave asks arbiter to remove allocation from master 50 Table 39 Address recognition proto
19、col (N=15) 51 Table 40 Address recognition protocol (N=23) 52 Table 41 Address recognition protocol (N=31) 53 Table 42 Input/output connector A 57 Table 43 Input/output connector B 58 Table 44 Minimal delays complying with timing requirements 63 Publications referred to Inside back coverBS6475:1984
20、iv BSI 02-2000 Foreword This BritishStandard was published under the direction of the Office and Information Standards Committee. It is based on the Eurobus A specification, published by the Ministry of Defence as Defence Standard00-20, and specifies the same interface. The text of this standard is
21、under consideration by the International Organization for Standardization (ISO) with a view to publication as ISO6951. For ease of production, Figure 1 to Figure 20 have been reproduced from Ministry of Defence Standard00-20, with alterations to Figure 2, Figure 5 and Figure 18, with the permission
22、of the Ministry of Defence. Certain conventions are not identical to those used in BritishStandards. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard
23、 does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an inside front cover, pagesi toiv, pages1to70, an inside back cover and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. Thi
24、s will be indicated in the amendment table on the inside front cover.BS6475:1984 BSI 02-2000 1 0 Introduction 0.1 General. This standard specifies the set of signal lines that constitute the bus itself, and the interfacing of devices connected to the bus. This standard specifies protocols for the al
25、location of bus time to devices wishing to make transfers and for the transfer of data between devices. The standard does not, however, specify priority rules, these being left to be formulated individually for each system. This standard specifies a full set of signalling rules to be followed by the
26、 device responsible for bus allocation and by devices conducting transfers. Appendix F gives illustrative examples of each of the possible types of transfer. The set of electrical and signal timing requirements specified in clause6 uniquely defines the interface that is Eurobus A. Certain mechanical
27、 requirements are specified in clause6, namely those that directly affect the electrical characteristics (e.g.the physical length of the bus, the spacing of device connectors on the bus, the pin pitch on connectors and the signal disposition on the connectors), but this standard does not further spe
28、cify the mechanical implementation. An example of a possible mechanical implementation of EurobusA is given in Appendix J. Implementations of Eurobus A are possible with8,16,24, 32, -bit data widths and devices having different data widths can operate on the same bus. Logical implementation summarie
29、s for the first four of the possible data widths are given in Appendix A to Appendix D. Appendix E specifies the connector allocation. The group of signal lines constituting an assembled Eurobus A provides the means for the transfer of binary digital information between up to20 devices plugged into
30、the backplane of a single equipment shelf. Devices share the bus on a time-division multiplex basis. The length of the backplane is limited to a maximum of460mm. The signal lines form an asynchronous unbalanced voltage interface capable of operating at transfer rates of up to6.5 10 6words or bytes p
31、er second. 0.2 Data width and addressing capability. The data/address width of any device using the bus is theoretically unconstrained. However, the asynchronous protocols and addressing facilities of Eurobus A permit devices of8,16,24 and32-bit data widths to share the same bus, and when the bus is
32、 so shared, the maximum data width is that of the widest device. The full addressing capability of the bus enables devices to address any8-bit byte of any word in a normal address space defined by both of the following. a) The addressing range determined by the number of data/address bits. b) A two-
33、bit extension to the foregoinga). The full two-bit extension is available on buses with non-shared width, but on shared-width buses the use of these bits is restricted. In addition, any complete word can be addressed in a second address space of equal magnitude to the first, designated the pseudo ad
34、dress space. 0.3 Devices. Free choice is available to the system designer as to the devices connected to a Eurobus and the order in which they are connected. However, each bus needs to include both: a) an arbiter, the purpose of which is to control the time-division multiplexing of transfers on the
35、bus; b) if communication with other buses if required, a bus link to each of the other buses. Figure 1 shows an example of a bus with a number of typical devices including an arbiter and a bus link. 0.4 Bus allocation. Information is transferred between devices on a master-and-slave basis. A device
36、bids for control of the bus by means of its starred Request line and becomes the master device for that transfer after the arbiter has allocated the bus to it. This standard specifies the protocols by which devices bid for use of the bus and by which the arbiter allocates the use of the bus to one o
37、f them. The standard does not, however, specify the algorithm used in making the selection, thus the system designer is given the choice of an allocation algorithm in order to optimize system performance. The protocol whereby a master device may flag an interrupt to the arbiter is also specified, bu
38、t the subsequent action by the arbiter is left to the system designer to define. 0.5 Bus transfers. In addition to specifying the protocols for the execution of Read cycles (in which the master addresses a device as slave and reads data from it) and Write cycles (in which the master transfers data t
39、o the addressed slave), this standard also specifies the protocol for a Vector cycle in which an address, without data, is transferred from master to slave. BS6475:1984 2 BSI 02-2000 The bus allocation protocols permit a master to hold the bus for repeated use without the need to make a fresh bit fo
40、r every transfer, while also giving the arbiter the ability to instruct any master to release the bus for reallocation. A master is also permitted to retain the bus for an indivisible sequence of cycles, such as a Read-Modify-Write sequence. An additional protocol is defined whereby the arbiter may
41、abort a cycle that is deemed to have failed. 0.6 Interbus transfers. The protocols for Read, Write and Vector cycles permit a master on bus A, for example, wishing to effect a transfer with a slave on bus B, to address a bus linker on bus A as slave. The bus linker then bids for use of bus B as mast
42、er and addresses the required slave on bus B. Should master devices on both buses attempt simultaneous transfers, the bus link cannot become master on either bus and a condition of deadly embrace ensues. The Eurobus protocols permit the embrace to be broken simply. The protocols used by bus links to
43、 perform interbus addressing and data transfer are not within the scope of this standard. 0.7 Electrical requirements. The standard specifies the electrical and timing requirements that need to be obeyed by Eurobus A devices. Aspects covered within the electrical requirements include: a) the voltage
44、 levels of the active and quiescent logic states on the bus; b) the required characteristics of the terminations networks; c) the required characteristics of the bus transmitters and receivers; d) the required characteristics of the spurs to be connected to the bus. The specified set of electrical c
45、haracteristics presupposes certain bus settling times for the transitions on the signal lines. Arising from these, certain timing constraints are specified. These constraints ensure that the relevant signal lines will have settled to the appropriate state before an associated control signal transiti
46、on is issued. NOTEReproduced with permission of Ministry of Defence from Ministry of Defence Standard00-20. Figure 1 Eurobus with some typical devicesBS6475:1984 BSI 02-2000 3 0.8 Commercial and military versions. Two versions of Eurobus A are specified in this standard, a version for a commercial t
47、emperature range(0Cto70 C) and a version for a military temperature range(55 C to125 C). Where the requirements are different they are separately specified for each version. 1 Scope This BritishStandard specifies a processor system bus interface known as Eurobus A that is one of a family of interfac
48、es for use in modular data acquisition, communication and control systems for military, industrial and other applications. NOTE 1More detailed information about the requirements specified in this standard, including the data width and addressing capability, devices connected to the bus, bus allocati
49、on, bus transfers, interbus transfers and electrical requirements, and background information are given in clause0. NOTE 2In this standard, upper case letters are used for the first letter of names of bus cycles. NOTE 3The titles of the publications referred to in this standard are listed on the inside back cover. 2 Definitions For the purposes of this BritishStandard the following definitions apply. 2.1 address the location of a data
