1、Format for LSI-Package-Boardinteroperable designBS IEC 63055:2016BSI Standards PublicationWB11885_BSI_StandardCovs_2013_AW.indd 1 15/05/2013 15:06National forewordThis British Standard is the UK implementation of IEC 63055:2016. The UK participation in its preparation was entrusted to TechnicalCommi
2、ttee EPL/501, Electronic Assembly Technology.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions ofa contract. Users are responsible for its correct application. The British Standar
3、ds Institution 2016.Published by BSI Standards Limited 2016ISBN 978 0 580 94227 3ICS 31.180; 31.200; 35.060Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of theStandards Policy and Strategy Committee on 30 Novem
4、ber 2016.Amendments/corrigenda issued since publicationDate Text affectedBRITISH STANDARDBS IEC 63055:2016IEC 63055 Edition 1.0 2016-11 INTERNATIONAL STANDARD Format for LSI-Package-Board interoperable design INTERNATIONAL ELECTROTECHNICAL COMMISSION ICS 31.180; 31.200; 35.060 ISBN 978-2-8322-3686-4
5、 Warning! Make sure that you obtained this publication from an authorized distributor. IEEE Std 2401 Registered trademark of the International Electrotechnical Commission BS IEC 63055:2016Contents 1. Overview 1 1.1 Scope . 1 1.2 Purpose 1 1.3 Key characteristics of the LSI-Package-Board Format 1 1.4
6、 Contents of this standard . 3 2. Normative references 3 3. Definitions, acronyms, and abbreviations 3 3.1 Definitions . 3 3.2 Acronyms and abbreviations . 6 4. Concept of the LPB Format 8 4.1 Technical background 8 4.2 Conventional design 8 4.3 Common problems at the design site . 8 4.4 Concept of
7、LPB interoperable design 9 4.5 Value creation by LPB interoperable design . 9 4.6 LPB Format 10 4.7 Summary of LPB Format files 10 5. Language basics.16 6. Common elements in M-Format, C-Format, and R-Format 17 6.1 General .17 6.2 The element 18 6.3 The element .19 7. M-Format.31 7.1 M-Format file s
8、tructure.31 7.2 The element .31 7.3 The element .32 8. C-Format .36 8.1 C-Format file structure .36 8.2 The element .37 8.3 The element .82 9. R-Format .86 9.1 R-Format file structure .86 9.2 The element .86 9.3 The element 116 10. N-Format .122 10.1 Purpose of the N-Format file 122 10.2 How to iden
9、tify the power/ground network 122 10.3 Example 122 11. G-Format .122 11.1 Language basics of G-Format .122 11.2 Structure .123 IEC 63055:2016 IEEE Std 2401-2015 i BS IEC 63055:201611.3 Header section 124 11.4 Material section 125 11.5 Layer section.126 11.6 Shape section 126 11.7 Board geometry sect
10、ion 131 11.8 Padstack section 133 11.9 Part section .134 11.10 Component section .135 11.11 Net attribute section 136 11.12 Netlist section .136 11.13 Via section 138 11.14 Bondwire section 139 11.15 Route section 141 Annex A (informative) Bibliography 145 Annex B (informative) Examples of utilizati
11、on 146 B.1 Understanding the function of the LPB Format .146 B.2 Test bench 146 B.3 Design flow example .148 B.4 Growth of the sample files in the LPB Format 179 B.5 Simulations using the sample files in the LPB Format 182 Annex C (informative) XML Encryption 184 Annex D (informative) MD5 checksum 1
12、87 Annex E (informative) Chip-Package Interface Protocol 188 E.1 General .188 E.2 Comparison of C-Format with Chip-Package Interface Protocol .188 Annex F (informative) IEEE list of participants .194 IEC 63055:2016 IEEE Std 2401-2015 ii BS IEC 63055:2016FORMAT FOR LSI-PACKAGE-BOARD INTEROPERABLE DES
13、IGN)25(:25 7KH,QWHUQDWLRQDO(OHFWURWHFKQLFDO design tools can use it to exchange information/data seamlessly. Keywords: common interoperable format, components, design analysis, design rules, geometries, IEEE 2401, large-scale integrated circuits, netlists, packages for LSI circuits, printed circuit
14、board, project management, Verilog-HDL xIEC 63055:2016 IEEE Std 2401-2015 vii BS IEC 63055:2016I(,ntroduction This introduction is not part of IEEE Std 2401-2015, IEEE Standard Format for LSI-Package-Board Interoperable Design. To deal with the increasing difficulty of design and the cost competitiv
15、eness of the global market, and to shorten the development term, innovative design methodologies should be implemented. It has been difficult to achieve the optimization of an entire set of large-scale integrated (LSI) circuits, packages, and board (LPB) using individual design processes for each LP
16、B part. One possibility for optimization is to have a certain section design the whole LPB; however, gathering knowledge and integrating the design environment of each LPB part is difficult. Dedicated professional technicians of individual LPB parts, who have the best knowledge and performance of th
17、eir own parts design tools, intend to create design optimization by having proper interoperable information exchanges among all LPB parties. In order to achieve a design that optimizes the balance between cost and performance, information about and the results of design should be well shared among c
18、ooperating LPB design sections. The Japan Electronics and Information Technology Industries Association (JEITA) LPB Interoperable Design Process Working Group (LPB-WG) was established to identify the solution. The LPB-WG intends to make a standard for an exchange format to make it easy to exchange i
19、nformation between each of the LPB design departments, so that optimal design will be carried out quickly. The LPB interoperable design process has the following issues: Netlist not unified on each LPB Complexity of the representation of the relationship as a whole arrangement of the LPB Differences
20、 in how to give the design constraints, lack of design information, and many discrepancies in design rules. Databases not unified in each LPB, or among different vendors No unified terms Various problems caused by these issues include the following: A large effort is required for conversion of forma
21、ts. The occurrence of conversion errors and connection errors is difficult to detect because there is a lack of the information needed to do so. It takes a long time to gather information, resulting in a long period of design and analysis. It is difficult to make optimal design changes because the e
22、ntire verification process is difficult. EDA tool cost increase because of additional development required to support multiple formats. It is time-consuming for designers to communicate their intentions in a way that others understand. Based on this analysis, the LPB-WG has established an interface
23、format that can address these issues. As the one of the case studies of the LPB interoperable design process, the power distribution network (PDN) should be designed with information about the other LPB parts to reduce the noise (see Figure i). IEC 63055:2016 IEEE Std 2401-2015 viii BS IEC 63055:201
24、6Reprinted with permission from JEITA. Figure iPower distribution network Resonance is caused by a capacitance and inductance present in the various parts in the LPB PDN. Impedance at the resonant frequency will be extremely large. If each part of the overall LPB design is not accurately simulated i
25、n the PDN model, the power supply circuit cannot be correctly designed (see Figure ii). Reprinted with permission from JEITA. Figure iiExample of PDN impedance In order to run properly, this simulation should align a variety of information, such as the circuit model of power distribution network (PD
26、N) of LSI, shape information about the package and board, electrical parameters of materials, and models of the components. It is difficult to make an efficient design when the specification or format of the design information is different in each part of the LPB, and the necessary parameters are no
27、t shared. When the format of the interface methods and models of the simulation are not consistent, the setup time and the cost of design/verification are enormous, which has become a barrier to cooperation in LPB design. The LPB-WG was established in JEITA to explore ways to create a mutual LPB int
28、erface to enable a more efficient co-design environment. IEC 63055:2016 IEEE Std 2401-2015 ix BS IEC 63055:2016Format for LSI-Package-Board Interoperable Design IMPORTANT NOTICE: IEEE Standards documents are not intended to ensure safety, security, health, or environmental protection, or ensure agai
29、nst interference with or from other devices or networks. Implementers of IEEE Standards documents are responsible for determining and complying with all appropriate safety, security, environmental, health, and interference protection practices and all applicable laws and regulations. This IEEE docum
30、ent is made available for use subject to important notices and legal disclaimers. These notices and disclaimers appear in all publications containing this document and may be found under the heading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.” They can also be
31、 obtained on request from IEEE or viewed at http:/standards.ieee.org/IPR/disclaimers.html. 1. Overview 1.1 Scope This standard defines a common interoperable format that will be used for the design of a) large-scale integration (LSI), b) packages for such LSI, and c) printed circuit boards on which
32、the packaged LSI are interconnected. Collectively, such designs are referred to as” LSI-Package-Board” (LPB) designs. The format provides a common way to specify information/data about the project management, netlists, components, design rules, and geometries used in LPB designs. 1.2 Purpose The gen
33、eral purpose of this standard is to develop a common format that LPB design tools can use to exchange information/data seamlessly, as opposed to having to work with multiple different input and output formats. 1.3 Key characteristics of the LSI-Package-Board Format LPB format will facilitate the exc
34、hange of design information. This functionality provides the ability to plan the entire design at an early stage. In effect, post-design analysis will be possible throughout the entire IEC 63055:2016 IEEE Std 2401-2015 1 BS IEC 63055:2016LPB design process. Analysis of each part of the design can be
35、 examined in relation to all other parts of the design, to determine the optimal point to give feedback for appropriate design changes throughout the LPB. This will promote the overall optimization of the design process. The LPB Format is constructed out of the following five formats (see Figure 1):
36、 a) Project Manage (M-Format) b) Netlist (N-Format) c) Component (C-Format) d) Design Rule (R-Format) e) Geometry (G-Format) Reprinted with permission from JEITA. Figure 1 LPB Format Design time can be shortened by using the LPB Format. Traditionally, design starts immediately after separate plannin
37、g for each individual component of the LPB. Therefore, information exchange among the separate design processes is limited. Trying to adjust the detailed design of one component to the detailed design of another component makes the entire design period take longer. Optimization also tends to be a se
38、parate process for each component of the LPB. By using the LPB Format for distributing information, each LPB technician will be able to have the same understanding of the challenges at an early stage. As a result, adjustments at the conceptual design stage can be made, before detailed designs are de
39、veloped. By making clear the overall LPB product specifications, the design target can be decided, and so the duration of individual designs can be shortened. Use of the LPB Format also helps to reduce the number of design iterations, because the design quality is enhanced. The designers can collect
40、 all information for simulation IEC 63055:2016 IEEE Std 2401-2015 2 BS IEC 63055:2016using the LPB formats, thereby reducing production time. The LPB Format can enable the entire analysis easily, so that sufficient verification can be done and the quality of the products can be improved. As a result
41、, the period of adjustment in the set can be shortened and the time to market can be accelerated. With the LPB Format, the design method for one product can be applied to the design environment for next product in development. 1.4 Contents of this standard The organization of the remainder of this s
42、tandard is as follows: Clause 2 provides references to other applicable standards that are presumed or required for this standard. Clause 3 defines terms and acronyms used throughout the different specifications contained in this standard. Clause 4 describes the concepts of the LPB Format. Clause 5
43、describes the language basics for the LPB Format and its commands. Clause 6 describes common elements in the M-Format, C-Format, and R-Format. Clause 7 describes the M-Format. Clause 8 describes the C-Format. Clause 9 describes the R-Format. Clause 10 describes the N-Format. Clause 11 describes the
44、G-Format. 2. Normative references The following referenced documents are indispensable for the application of this document (i.e., they must be understood and used, so each referenced document is cited in text and its relationship to this document is explained). For dated references, only the editio
45、n cited applies. For undated references, the latest edition of the referenced document (including any amendments or corrigenda) applies. IEEE Std 1364, IEEE Standard for Verilog Hardware Description Language.1,23. Definitions, acronyms, and abbreviations 3.1 Definitions For the purposes of this docu
46、ment, the following terms and definitions apply. The IEEE Standards Dictionary Online should be consulted for terms not defined in this clause.31IEEE publications are available from The Institute of Electrical and Electronics Engineers (http:/standards.ieee.org/). 2The IEEE standards or products ref
47、erred to in this clause are trademarks of The Institute of Electrical and Electronics Engineers, Inc. 3IEEE Standards Dictionary Online subscription is available at: http:/www.ieee.org/portal/innovate/products/standard/standards_dictionary.html. IEC 63055:2016 IEEE Std 2401-2015 3 BS IEC 63055:2016a
48、ntipad: The clearance hole between a via and a no-connect metal layer, mainly used on the printed circuit board and LSI package. The shape of the antipad is mainly determined by the limit on the printed circuit board or LSI package manufacturing and is defined by the padstack in the R-Format file. b
49、all grid array (BGA) package: A type of surface-mount package with one face covered (or partly covered) with solder balls arranged in a grid pattern. ball: See: solder ball. board: The printed circuit board or printed wiring board. bonding finger: The metal electrode on the surface of an LSI package. It connects the bonding wire to the routing pattern on the LSI package. In LPB Format files, the shape of the bonding fing
