1、DESC-DWG-87685 57 I 7777775 0030474 7 I LTR DESCRIPTION DATE APPROVED . Defense Electronlcs Supply Center Dayton, Ohlo Orlglnal date of drawing: 9 November 1987 AMSC NIA MILITARY DRAWING This drawing is available for use by all Departments and Agencies of the Deoartment of Defense MICROCIRCUITS, B-B
2、IT MICRO- TITLE: PROCESSOR CPU, NMOS, MONOLITHIC 5962- 87685 SIZE CODE IDENT. NO. DWG NO. A 67268 REV PAGE 1 OF 22 I SY62-tS36 I DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. DESC FORM 193 MAY 86 Provided by IHSNot for ResaleNo reproduction or networking permitted
3、 without license from IHS-,-,-? 1. SCOPE 1 1 SCO e .2:1 oemperature range. 3.4 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall be narked with the part number listed in 1.2 herein. In addition, the manufacturers part number may also )e marked as listed in 6.5
4、 herein, 3.5 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in wder to be listed as an approved source of supply in 6.5. The certificate of compliance submitted to )ESC-ECS prior to listing as an approved source of supply shall state that the manufacture
5、rs product neets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements herein. ierein) shall be provided with each lot of microcircuits delivered to this drawing. 3.6 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1 3.7 Notification of chan
6、ge. Notification of change to DESC-ECS shall be required in accordance with IL-STD-883 ( see 3.1 herein). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE MILITARY DRAWING A DWG NO. 5962-87685 DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO REV PAGE
7、4 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical performance characteristics - Continued. I I I I I I subgroups 1-1 I l 4.5 v K INVALID ADDRESS SOFTWARE HALT BUS TIMING-MINIMUM MODE SYSTEM (CONTINUED) SIZE MILITARY DRAWING A t DW
8、G NO. 5962-87685 WHDX DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO REV PAGE 13 NOTES: 1, All signals swi ch between VO and VOL unless otherwise specified. 2. RDY is sampled near the end o! Tp, T3, TW to determine if TW machines states are to be inserted. 3. Two INTA cycles run back to back. The 80
9、88 local ADDR/DATA bus is floating during both INTA cycles. 4. Signals at 8284 are shown for reference only. 5. All timing measurements are made at 1.5 V unless otherwise noted. Control signals are shown for the second INTA cycle. t- Provided by IHSNot for ResaleNo reproduction or networking permitt
10、ed without license from IHS-,-,-_ - DESC-DWG-87685 57 7777775 OOL057 L . BUS TIMING- MAXIMUM MODE SEE NOTE 5 -I - s2, SI sg (EXCEPT HALT A -A 15 8 - 4 Aids6-ks3 ALE (8288 OUTPUT) GKT RDY (8284 INPUT) c I READY (8088 INPUT) -4 ,- - See notes on next page. FIGURE 4. Switching waveforms - Continued. MI
11、LITARY DRAW1 N G DEFENSE ELECTRONICSSUPPLYCENTER DAYTON, OHIO DESC FORM 193A FEE 86 SIZE DWG NO. A 5962-87685 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I 1 DESC-DWG-87685 57 I 9777775 0020508 3 W MILITARY DRAW1 N G DEFENSE ELECTRONICS SUPPLY CE
12、NTER DAYTON, OHIO BUS TIMING-MAXIMUM MODE SYSTEM (USING 8288) A 5962-87685 REV PAGE 15 8288 OUTPUTS SEE NOTES 56 DEN OR AIOWC 4 14bLML* 4- MWTC OR m - - 7l OUTPUTS SEE NOTES 5Y6 + I A I I - - NOTES : s2 S, sg - - 1. All signals switch between VOH and VOL unless otherwise specified. 2. RDY is sampled
13、 near the end of Te, T3, TW to determine if TW machines states are to be inserted. 3. Cascade address is valid between first and second INTA cycles. 4. Two INTA cycles run back to back. during both INTA cycles. INTA cycle. 5. Signals at 8284 or 8288 are shown for reference only. 6. The issuance of t
14、he 8288 command and control signals (m, m, m, m, m, my m, and DEN) lags the active high 8288 CEN. 7. All timing measurements are made at 1.5 Y unless otherwise noted. 8. Status inactive in state just prior to T4. The 8088 local ADDR/DATA bus is floating Control for pointer address is shown for secon
15、d FIGURE 4. Switching waveforms - Continued. I SIZE I I DWGNO. DESC FORM 193A FEB 6 t i Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - - -_ DESC-DWG-87b5 59 7,77775 0010507 5 H ASYNCHRONOUS SIGNAL RECOGNITION BUS LOCK SIGNAL TIMING (MAXIMUM MODE
16、ONLY) CLK NMI 7EST ANY NOTE I) ANY -e . _ . I NOTE : 1. Set-up requirements for asynchronous signals only to guarantee recognition at next CLK. REQUESTIGRANT SEQUENCE TIMING (MAXIMUM MODE ONLY 1 NOTE : 1. The coprocessor may not drive the buses outside the region shown without rising contention. HOL
17、D/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY) HLDA . .pecifications do not exist and qualified military devices that will perform the required function are iot available for OEM application. When a military specification exists and the product covered by ;his drawing has been qualified for listing o
18、n QPL-38510, the device specified herein will be nactivated and will not be used for new desiyii. Ttie QPL-3d510 product shall be the preferred item for i1 1 applications. :overeK otherwise, the processor waits in an “idle“ state. This input is synchronized internally during each clock cycle on the
19、leading edge of CLK. I I I I I I 17 N MI i I i Noii maskable interrupt. An edge-triggered input which causes a I I type 2 interrupt. A subroutine is vectored to via an interrupt I I vector lookup table located in system memory. NM is not maskable I I internally by software. A transition from a LOW t
20、o HIGH initiates 1 I the interrupt at the end of the current instruction. This input I 1 is internally synchronized. 1 1 1 I I I 21 i RESET i I I I I I I I I I I I RESET. Causes the processor to imnediately terminate its present activity. The signal inust be active HIGH for at least four clock cycle
21、s. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized. I I I 19 CLK I i Clock. Provides the basic timing for the processor and bus I controller, 1 optimized internal timing. It is asymmetric with a 33 percent duty cycle to
22、 provide +- Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Y DESC-DWG-47645 57 m 7777775 0010514 7 m - .: SIZE MILITARY DRAWING A I I I I 11 I II I I I I I 1 in number 1 Name 1 1/0 1 Description 1 I VCC. The +5 V *lo% power supply pin. 40 I vcc 1, 2
23、0 I GND I I GND. The ground pins. DWG NO. 5962-87685 33 i MINm i I i Minimum/maximum. Indicates what mode the processor is to operate 1 I I in. The two modes are discussed in tne following sections. DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 1 1 I . I REV PAGE 21 28 I I I I IO/M I O I Status lin
24、e. An inverted maximum mode 32. It is used to 1 I I distinguish a memory access from an 1/0 access. IO/M becomes I I I valid in the T4 preceding a bus cycle and remains valid 1 1 I until ttie final T4 of tile cycle (I/O = HIGH, MII= LOW). IO/E floats I . 1 I to 3-state OFF in local bus “hold acknowl
25、edge. I II i 29 im 1 I 1 I I i O i Write. Strobe indicates that the processor is performiny a write I I memory orwrite 1/0 cycle, depending on the state of trie IO/R I I signal. Wl is active for T2,T3, and TW of aiy write cycle. I 1 It is active LOW and floats to 3-state OFF in local bus “hold 1 1 a
26、cknowledge“. I I I I l I I I It is active LOW during T2,T3and Tw of each interrupt 1 I I acknowledgement cycle. _ 24 I TNTK 1 O I INTA. Used as a read strooe for interrupt acknowledge cycles. I 1 I. 25 I I I 1 ALE I O I Address latcn endble. Provided by the processor to latch the I 1 I address into
27、8282/8283 address latch. It is a HIGH pulse active I I I during clock low of Ti of any bus cycle. Note that ALE is never I I I floated. I II I 27 1 DT/R I O I Data transmit/receive. Needed in a minimum system that desires I 1 I to use an 8286/8287 data bus transceiver. It is used to control I I I th
28、e direction of data flow through the transceiver. Logically DT/K is equivalent to Si in tne maximum mode, and its timing is I 1 1 I I 3-state OFF i n 1 oca1 bus “no1 d acknowledge“. 1 I I the same as for IO/R (T-HIGH, R-LOW). This signal floats to I 1 1 I 26 DEN i O i Data enable. Provided as an out
29、put enable for tne 8236/82 while for a write cycle, itisactive from the I 1 I I I 1 I OFF during local bus “hold acknowledge. 1 I I I beginning of Tp until the middle of T4. DtN floats to 3-state read or INTA cycle, it is active from tne middle of T2 until the Provided by IHSNot for ResaleNo reprodu
30、ction or networking permitted without license from IHS-,-,-6.4 Coriknents. Comnents on this drawing should be directed to DES(;-ECS, Dayton, Ohio 45444, or ;elephonec513-Z96-5375. 6.5 Approved source of supply. An approved source of supply is listed herein. Additional sources dl1 be added as they be
31、come avallable. The vendor listed herein has agreed to this drawing and a Zertificate of compliance (see 3.5 herein) has been submitted to DES-ECS. I I Vendor I Vendor I KepiaCeiWnt I I Military drawing I CAGE I similar part I military specification1 number 1/ I part number I I -1 I 1 I I I I 5962-8
32、76d5010X I 34335 i 1 I I I part number I ao88/eqA I I I I I I 1 - i/ Caution. Do nat use this number for item acquisition. Items acquired =numer may not satisfy the performance requirements of this drawing Vendor CAtiE number 34335 Vendor name and address Advanced Micro Devices, Incorporated 901 Thompson Place P.O. Box 3453 Sunnyvale, CA 94088 SIZE DWG NO. MILITARY DRAWING A 5962-87685 DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO REV PAGE DESC FORM 193A FEE 66 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
