1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationSemiconductor devices Mechanical and climatic test methodsPart 29: Latch-up testBS EN 60749-29:2011National forewordThis British Standard is the UK implementation of EN 60749-29:
2、2011. It isidentical to IEC 60749-29:2011. It supersedes BS EN 60749-29:2003 which iswithdrawn.The UK participation in its preparation was entrusted to Technical CommitteeEPL/47, Semiconductors.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publ
3、ication does not purport to include all the necessary provisions of acontract. Users are responsible for its correct application. BSI 2011ISBN 978 0 580 69138 6ICS 31.080.01Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the a
4、uthority of the StandardsPolicy and Strategy Committee on 31 August 2011.Amendments issued since publicationAmd. No. Date Text affectedBRITISH STANDARDBS EN 60749-29:2011EUROPEAN STANDARD EN 60749-29 NORME EUROPENNE EUROPISCHE NORM August 2011 CENELEC European Committee for Electrotechnical Standard
5、ization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Management Centre: Avenue Marnix 17, B - 1000 Brussels 2011 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 60749-29:2011 E I
6、CS 31.080.01 Supersedes EN 60749-29:2003 + corr. Mar.2004English version Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test (IEC 60749-29:2011) Dispositifs semiconducteurs - Mthodes dessai mcaniques et climatiques - Partie 29: Essai de verrouillage (CEI 60749-29:20
7、11) Halbleiterbauelemente - Mechanische und klimatische Prfverfahren - Teil 29: Latch-up-Prfung (IEC 60749-29:2011) This European Standard was approved by CENELEC on 2011-05-12. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving th
8、is European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versio
9、ns (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of A
10、ustria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the Unite
11、d Kingdom. BS EN 60749-29:2011EN 60749-29:2011 - 2 - Foreword The text of document 47/2083/FDIS, future edition 2 of IEC 60749-29, prepared by IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60749-29 on 2011-05-12. This European Stan
12、dard supersedes EN 60749-29:2003 + corrigendum March 2004. The significant changes with respect to EN 60749-29:2003 include: a number of minor technical changes; the addition of two new annexes covering the testing of special pins and temperature calculations. Attention is drawn to the possibility t
13、hat some of the elements of this document may be the subject of patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent rights. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identic
14、al national standard or by endorsement (dop) 2012-02-12 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2014-05-12 _ Endorsement notice The text of the International Standard IEC 60749-29:2011 was approved by CENELEC as a European Standard without any m
15、odification. _ BS EN 60749-29:2011 2 60749-29 IEC:2011 CONTENTS 1 Scope and object 5 2 Terms and definitions . 5 3 Classification and levels . 8 3.1 Classification . 8 3.2 Levels . 8 4 Apparatus and material 8 4.1 Latch-up tester 8 4.1.1 General . 8 4.1.2 Vsupplyand their qualification method. 9 4.1
16、.3 Trigger source qualification method . 9 4.2 Automated test equipment (ATE) . 10 4.3 Heat source . 10 5 Procedure 10 5.1 General latch-up test procedure 10 5.2 Detailed latch-up test procedure 13 5.2.1 I-test 13 5.2.2 Vsupplyovervoltage test 17 5.2.3 Testing dynamic devices . 19 5.2.4 DUT disposit
17、ion . 19 5.2.5 Record keeping . 19 6 Failure criteria 20 7 Summary 20 Annex A (informative) Examples of special pins that are connected to passive components 21 Annex B (informative) Calculation of operating ambient or operating case temperature for a given operating junction temperature 23 Figure 1
18、 Vsupplyqualification circuit 9 Figure 2 Trigger source qualification circuit 10 Figure 3 Latch-up test flow . 11 Figure 4 Test waveform for positive I-test 14 Figure 5 Test waveform for negative I-test . 15 Figure 6 Equivalent circuit for positive input/output I-test latch-up testing 16 Figure 7 Eq
19、uivalent circuit for negative input/output I-test latch-up testing . 17 Figure 8 Test waveform for Vsupplyovervoltage 18 Figure 9 Equivalent circuit for Vsupplyovervoltage test latch-up testing . 19 Figure A.1 Examples of special pins that are connected to passive components 22 Table 1 Test matrixa.
20、 12 Table 2 Timing specifications for I-test and Vsupplyovervoltage test . 13 BS EN 60749-29:201160749-29 IEC:2011 5 SEMICONDUCTOR DEVICES MECHANICAL AND CLIMATIC TEST METHODS Part 29: Latch-up test 1 Scope and object This part of IEC 60749 covers the I-test and the overvoltage latch-up testing of i
21、ntegrated circuits. This test is classified as destructive. The purpose of this test is to establish a method for determining integrated circuit (IC) latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are used in determining product reliability and minimizing
22、“no trouble found“ (NTF) and “electrical overstress“ (EOS) failures due to latch-up. This test method is primarily applicable to CMOS devices. Applicability to other technologies must be established. The classification of latch-up as a function of temperature is defined in 3.1 and the failure level
23、criteria are defined in 3.2 2 Terms and definitions For the purposes of this document, the following terms and definitions apply. 2.1 cool-down time period of time between successive applications of trigger pulses or the period of time between the removal of the Vsupplyvoltage and the application of
24、 the next trigger pulse (See Figures 4, 5, and 8 and Table 2.) 2.2 device under test DUT semiconductor product subjected to latch-up test 2.3 ground GND common or zero-potential pin(s) of the DUT NOTE 1 Ground pins are not latch-up tested. NOTE 2 A ground pin is sometimes called Vss. 2.4 input pins
25、all address, data-in control, Vrefand similar pins 2.5 I/O (bi-directional) pins device pins that can be made to operate as an input or output or in a high-impedance state BS EN 60749-29:2011 6 60749-29 IEC:2011 2.6 Isupplytotal supply current in each Vsupplypin (or pin group) with the DUT biased as
26、 indicated in Table 1 2.7 I-test latch-up test that supplies positive and negative current pulses to the pin under test 2.8 latch-up state in which a low-impedance path resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering c
27、ondition NOTE 1 The overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or any other abnormal condition that causes the parasitic thyristor structure to become regenerative. NOTE 2 Latch-up will not damage the device provided that the current through the
28、low-impedance path is sufficiently limited in magnitude or duration. 2.9 logic-high level within the more positive (less negative) of the two ranges of logic levels chosen to represent the logic states NOTE 1 For digital devices, a voltage level equal to Vsupplyis used for latch-up testing, except w
29、here otherwise specified in the relevant specification. NOTE 2 For non-digital devices, Vsupply voltage level or the maximum operating voltage that can be applied to that pin as defined in the relevant specification may be used for latch-up testing. 2.10 logic-low level within the more negative (les
30、s positive) of the two ranges of logic levels chosen to represent the logic states NOTE 1 For digital devices, ground voltage level is used for latch-up testing, except where specified in the relevant specification. NOTE 2 For non-digital devices, ground voltage level or the minimum operating voltag
31、e that can be applied to that pin as defined in the relevant specification may be used for latch-up testing. 2.11 maximum Vsupplymaximum operating voltage for operation within performance specifications NOTE 1 The maximum voltage is not the absolute maximum voltage beyond which permanent damage is l
32、ikely. NOTE 2 Maximum refers to the magnitude of Vsupplyand can be either positive or negative. 2.12 no connect pin pin that has no internal connection and that can be used as a support for external wiring without disturbing the function of the device NOTE All “no connect” pins should be left in an
33、open (floating) state during latch-up testing. 2.13 nominal Isupply(Inom) measured dc supply current for each Vsupplypin (or pin group) with the DUT biased at the test temperature as defined in Clause 5 and Table 1 BS EN 60749-29:201160749-29 IEC:2011 7 2.14 output pin device pin that generates a si
34、gnal or voltage level as a normal function during the normal operation of the device NOTE Output pins, though left in an open (floating) state during testing of other pin types, are latch-up tested. 2.15 preconditioned pin device pin that has been placed in a defined state or condition (input, outpu
35、t, high impedance, etc.) by applying control vectors to the DUT 2.16 testing of dynamic devices latch-up trigger testing of a device in a known stable state, at the minimum-rated clock frequency applied to the device (see 5.2.3 for specified conditions) 2.17 test condition test temperature, supply v
36、oltage, current limits, voltage limits, clock frequency, input bias voltages, and preconditioning vectors applied to the DUT during the latch-up test 2.18 timing-related input pin pin such as clock crystal oscillator, charge pump circuit, etc., required to place the DUT in a normal operating mode NO
37、TE Required timing signals may be applied by the latch-up tester, external equipment, and/or external components as appropriate. 2.19 trigger pulse positive or negative current pulse (I-Test) or voltage pulse (Vsupplyovervoltage test) applied to any pin under test in an attempt to induce latch-up (s
38、ee Figures 4, 5 and 8) 2.20 trigger duration duration of an applied pulse from the trigger source (see Figures 4, 5 and 8 and Table 2) 2.21 Vsupplypin (or pin group) all DUT power supply and external voltage source pins (excluding ground pins), including both positive- and negative-potential pins NO
39、TE 1 Generally, it is permissible to treat equal potential voltage source pins as one Vsupplypin (or pin group) and connect them to one power supply. NOTE 2 When forming Vsupplypins (or pin groups), the combination of Vsupplypins with significantly different supply current levels is not recommended
40、as this would make it difficult to detect significant current changes on low supply current pins. 2.22 Vsupplyovervoltage test latch-up test that supplies overvoltage pulses or overvoltage d.c. level to the Vsupplypin under test 2.23 Vsupplyvoltage level applicable voltage level of the Vsupplypin sp
41、ecified in the relevant specification. The Vsupplyvoltage level is used for latch-up testing as the typical logic high level unless otherwise specified (see 2.9) BS EN 60749-29:2011 8 60749-29 IEC:2011 2.24 ground voltage level ground potential used for latch-up testing as the typical logic low leve
42、l, unless otherwise specified (see 2.10) 3 Classification and levels 3.1 Classification There are two classes for latch-up testing. Class I is for testing at room temperature ambient. Class II is for testing at the maximum operating ambient temperature (Ta) or maximum operating case temperature (Tc)
43、 or maximum operating junction temperature (Tj) in the detailed specification. For Class II testing at the maximum operating Taor Tc, the ambient temperature or case temperature (Tc) shall be established at the required test value. For Class II testing at the maximum operating Tj, the ambient temper
44、ature Taor the case temperature Tcshould be selected to achieve a temperature characteristic of the junction temperature for a given device operating mode(s) during latch-up testing. The maximum operating ambient or case temperature during stress may be calculated based on the methods detailed in An
45、nex B. NOTE Elevated temperature will reduce latch-up resistance, and class II testing is recommended for devices that are required to operate at elevated temperature. 3.2 Levels Level defines the I-test current injection value used during latch-up testing. Latch-up passing levels are defined as fol
46、lows: Level A The trigger current value in Table 1 shall be +100 mA as defined in Figure 6 and -100 mA as defined in Figure 7. If all pins on the part pass at least the Level A trigger current values, then the part shall be considered a Level A part. Level B If any pins on the part do not pass the L
47、evel A standard, then the supplier shall determine the minimum passing trigger current requirement for each pin stressed differently than in Level A. The maximum (or highest) passing trigger current value shall be reported in the record for each pin stressed differently than in Level A, and the part
48、 shall be considered to be a Level B part, see 5.2.5. 4 Apparatus and material The apparatus required for this test method includes the following. 4.1 Latch-up tester 4.1.1 General Test equipment capable of performing the tests as specified in this standard. For devices requiring dynamic testing, th
49、e test equipment shall be capable of supplying timing signals and logic setup vectors required to control the I/O pin output states as specified in 5.2.3. The required timing signals and logic vectors may be applied by the latch-up tester itself, external equipment, and/or external components as appropriate. BS EN 60749-29:201160749-29 IEC:2011 9 4.1.2 Vsupplyand their qualification method For the I-test, sink type voltage power supplies shall be connected to all V
