1、EIA JESDLZ-LB 93 m 3234600 0509b23 LT7 m Ikproducad y GLOBAL ENGINEERING DOCUMENTS WRh Thr hission d EIA ndn Royalty Agrement JEDEC STANDARD Terms and Definitions for Gate Arrays and Cell-Based Digital Integrated Circuits JESD12-1 B (Revision of JEDEC Standard No. 12-1A) AUGUST 1993 ELECTRONIC INDUS
2、TRIES ASSOCIATION ENGINEERING DEPARTMENT I EIA JESDL2-LB 93 m 3234600 0507624 033 m NOTICE JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel.
3、 JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper pro
4、duct for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members
5、, whether the standard is to be used either domestically or internationally. JEDEC Standards and Publications are adopted without regard to whener their adoption may involve patents or articles, materials, or processes. By such action, JEDEC does not assume any liability to any patent owner, nor doe
6、s it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the J
7、EDEC organization there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately became an EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard should be addressed to the JEDEC Executive Secretafy at EIA Headquarters,
8、 2001 Pennsylvania Ave., N. W., Washington, D.C. 20006. Published by ELECTRONIC INDUSTRIES ASSOCIATION 1993 Engineering Department 2001 Pennsylvania Ave., N.W. Washington, D.C. 20006 PRICE Please refer to the current Catalog of EIA INVERTERS; LATCHES; MULTIPLEXER; AND FLIPFLOPS. 5. JESD 12-4 - Adden
9、dum No. 4 to JESD12, Method of Specification of Performance Parameters for CMOS Semicustom Integrated Circuits (April, 1987) c This Standard defines how to specify various performance parameters of semicustom ICs, including cell and interconnect propagation delays, input output levels and capacitanc
10、e, and power dissipation. J EIA JESDL2-LB 93 m 3234b00 0509b40 2b m JEDEC STANDARD NO. 12-1B Page 15 Appendix A (continued) Related Docunients 6. JESD 12-5 - Addendum No. 5 to JESD12, Design for Testability Guidelines (August, 1988) Provides descriptions of digital testability problems, solutions, t
11、erms and definitions and description of industry-standard approaches to structured testability. Also provides a bibliography of testability papers and books recommended as references by committee members. 6. JESD12-6 - Addendum No. 6 to JESD12, Interface Standard for Semicustom Integrated Circuits (
12、March, 1991) This Standard defines logic interface levels for CMOS, ITL, ECL, and BiCC inputs and outputs. This standard is intended to provide an industry-wide set of specifications, for Application Specific Integrated Circuit (ASIC) signal inputs and outputs, both necessary and sufficient to define a circuits electrical interfacing with the external environment.
