1、i i FEBRUARY 1986 JEDEC STANDARD NO. 12-2 STANDARD F OR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SET JEDEC Solid State Products Engineering Council EIA JESDL2-2 86 3234600 0004802 I m I NOTICE This JEDEC Standard or Publication contains material that has been prepared, progressively reviewed, and app
2、roved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvem
3、ent of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standard
4、s, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. Recommended Standards are adopted by JEDEC without regard to whether or not their adoption may involve patents or artic
5、les, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approach to produc
6、t specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures, whereby a JEDEC Standard or Publication may be further processed and ultimately become an EIA Ctandard. Inquiries, comments, and suggestions relative t
7、o the content of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. Published by ELECTRONIC INDUCTRIES ACCBCIATION Engineering Department 2001 Eye Ctreet, N.W. Washington, D.C. 20006 Copyright 19
8、86 ELECIRONIC 1”RIES ASaBcIATIQN PRICE: $14.00 s EPA JESD12-2 6 3234600 0004803 3 m JEDEC Standard No. 12-2 STANDARD FOR CELL-BASED INTEGRATED 61RCUIT BENCHMARK SET TABLE OF CONTENTS Paragraph Page 1.0 PURPOSE L 2.0 RELATED DOCUMENTS L 3.0 REASONS POR REQUIREMENT 1 4.0 VENDOR PRESENTATION OP DATA 2
9、4.1 Performance Bata 2 4 . 2 Performance Results 2 4.3 Specified Paxameters 2 %.BI INDEX OF BENCHMARKS 3 L NOTE: BENCHMARKS #i - #9 can be found in JEBEC Standard No. 12. BENCHMARKS #I0 - #,I6 are contained in this Standard as listed below: BENCHMARK #I63 BENCHMARK #la BENCHMARK #i2 BENCHMARK #13 BE
10、NCHMARK. #a4 BENCHMARK #15 BENCHMARK #a6 256 x 4 and 256 x 9 W/W Random Access Elemsry 5 similar to 21Ib 16 X 4 ROM Patch 6 2K x 4 and 2K a 9 Read Only Memory 4 Small and Large PLAIS 8 %:1 AnaLog Multiplexer 9 Comparator 22 8 Bit D/A 28 o - F EIA JESDL2-2 b m 3234bOI3 0004804 5 m JEBEC St.anda%d No.
11、 12-2 Page 1 STANDARD POR C33LL-BASED INTEGRATED CIRCUIT BENCHMARK SET (From JEDEC Council Ballot JCB-85-14, fsrmuP.ated under the cognizance of 56-44.2 Committee on Ce%l-Baeed Integrated Circuits.) 1.0 PURPOSE 2.0 The purpose of these benchmarks is to provide a common set of high-level functions to
12、 serve as vehicles for comparing the performance of cell-based ICs implemented in any technology using any internal structure. These benchmarks effectively provide an unbiased measure of vendors ability to implement a dezjiedl complex function at a known level of performance. I RELATED DOCUMENTS 3.8
13、 In addition %o this Standard, the following related JEBEC Standards are available: JEBEC Standard No. 12 Semisustorn integrated Cicuits, (May 1985) ; JEBEC Standard No. 12-1 semicustom Integrated ivxiis - erms and Definitions for Gate Arrays and Gell-Based Integrated Circuits (August 1985). REASONS
14、 POW REQUIREMENT Users of cell-based technology encounter a great deab of difficulty in developing estimates of realistic performance measures or potential designs. This is because most performance data currently specified by industry vendors exists at SSI level (viz NAND, NOR, INVERTER), Users need
15、 to know in advance of beginning a design the estimated perfomance o6 some commonly used MSI functions such as counters, decoders, octal flip-flops, small ALUS, etc. FEom this data they are able to construct an estimate of performance o6 critisal portions of their designs and check the feasibility O
16、f building that circuit using a specified cell-based technology. JEDEC Standard No. 12-2 Page 2 4.0 VENDOR PRESENTATION OF DATA While it is by no means mandatory khat cell-based IC vendors provide this data, a JEDEC standard benchmark inherently provides more consistency and structure in the marketp
17、lace, which is advantageous to both vendors and users. 4.1 Performance Data Vendors may choose to provide their customers with such performance data based purely on simulated designs or alternatively choose to implement macro element portions of test chips which they may then characterize and/or mak
18、e available to customers for evaluation. 4 . 2 Performance Results In all cases these performance results and parameters must specify the conditions and methods under which they are derived. Wherever multiple ac paths are possible from an input to an output, the vendor will specify the characteristi
19、cs of the slowest path. 4.3 Specified Parameters Parameters specified should include, but are not limited tor (1) Two-input gate equivalents or, where appropriate, (2) area, width, height; component count used; (3) worst-case dynamic power at vendor-specified frequency ( ies) and f anout; (4) dc sta
20、tic power with inputs at levels specified by vendor and at vendor-specified power supply voltage and temperature; (5) worst-case ac performance parameters for each benchmark cell, under vendor-specified power supply voltage, temperature and driving pulse edge rates; (6) method of implementation (har
21、d macro or soft macro) ; c EIA JESD12-2 86 W 3234600 0004806 9 W NOTE 1: CAUTION: JEDEC Standard MO. 12-2 Page 3 4.3 Specified PaKametera (continued) (7) number: of feedthroughs included in cell.; (8) separat (9) degree of eharaeterization (simulation specify whether with or without layout parasitic
22、s included , fabricated and measured silicon). All benchmark cells must be SmpPementabPe in a single IC process feasible for comercial introduction. For an actual. chip deign, total chip area is a function of both eel% area and routing area. Routing area is dependent on chip archi%ec%ure, layout: an
23、d specific application software. INDEX OF BENCHMARKS #i #Z #3 #4 #5 #6 #4 #8 #9 4 Bit ALU, similar to 948389. See Benchmark No. 1, JEDEC Standard NO. 12. See Benchmark No, 4 Bit astator see Benchmark No. 16 Bit Wokator BenChHiaKk NOs 16 Bit ALU, similar to 74838% 2, JEBEC Stamdard No. 12. 3, JEDEC S
24、tandard No. 1%. 4, JEBEC Standard No, 12. 8 Bit Register, a-rnilar to 748374 See Benchmark No. 5# JEDEC Standard No. 12. 8 Bit Up/Dswn counter . See Benchmark No. 4, JEDEC Standard No. 12. 3 to 8 Beeodemi, similar to 748138 See Beinckimak No. 7, JEDEC Standard No. 1%. 16x4 RAM, similar ta 748%9 See
25、Benchmark No. 8, JEDEC Standard No. 12. 9 it Parity enegaitor simi%ar to 74828a See Benchmark No. 9, JEDEC Standard No. 12. -_ EIA JESDL2-2 b 3234b00 0004807 O JEDEC Standard No. Page 4 5.0 INDEX OF BE This Standar No. 12-2, contains the below listed Benchmarks: #i0 256 x 4 56 x 9 RAM, similar to 21
26、01 #ll 16 X 4 RO #12 2K x 4 and #13 Small and #14 2:l A #15 Analog Comp #16 8 Bit Digital/Analog Converter. a EIA JESDL2-2 8b m 3234b00 0004808 2 m JEDEC Standard No. 12-2 O BENCHMARK #i0 Page 5 . 256 x 4 and 256 x 9 R/W RANDOM ACCESS MEMORY SIMILAR .TO 2101 Tests the cost/efficiency of nibble and b
27、yte (plus parity) wide memory functions. 256 X 9 RAM 8 The minimum performance parameters to be specified are: Max Delay Max Delay Max Delay Minimum Setup Minimum Setup Minimum Hold Minimum Setup Minimum Hold Any A to Any Y CS to Any Y OE to Any Y CS before WELOW - - - A before WE - Low A after WE R
28、ising Edge D before WE.Rising - Edge D after WE Rising Edge Minimum =Pulse Width a Total cells used/area/derating factor for layout. EIA JESDL2-2 86 m 3234600 O004809 4 m JEDEC Standard No. 12-2 Page 6 BENCHMARK 911 16 x 4 ROM PATCH Tests costjefficiency of a small .ROM that would be used for logic
29、patch purposes and would be -% AD- 4 cs CHIPSELECT- 16. X 4 m The minimum performance parameters to be specified are: Max Delay Any A to Any Y I Max Delay CS to Any Y Minimum Hold Total cells used/area used/derating factor for ,layout. Any A Change to Any Y Change I c EIA JESDL2-2 8b m 3234b00 00048
30、10 O m I Ao- Alo . AMIRESS 11 cs CHIP SELSCT . JEDEC Standard No. 12-2 Page 7 1. 4 yo - Y3 b. 4 . 1- DATAOVT 2048 X 4 Fa BENCHMARK #i2 Ao - ADDRESS # 11 * cs CHIPSELECT 2K x 4 and 2K x 9 READ ONLY MEMORY L DATA OUT yo - T. 2048 X 9 . RCM Tests the cost/efficiency of pr.ogram ROM that may be proqramm
31、ed either at the diffusion or interconnect level. .The minimum performance parameters to be specified are: Max Delay Any A to Any Y Max Delay CS to Any Y Minimum Hold Any A Change to Any Y Change Total cells used/area used/derating factor for layout Level at which the ROM is programmed (i.e. diffusi
32、on or interconnect). JEDEC Standard No. 12-2 Page 8 BENCHMARK 413 SMALL AND LARGE PLAs REQUIREMENTS Inputs Product Terms 16 32 48 256 outputs 8 20 No Folding Non-Reg is ter ed No Partioning Specify in addition to standard parameters: Static or synchronous operation; Speed on slowest path. e Programm
33、 i ng Level Metal Early (e.g. diffusion) O JEDEC Standard No, 12-2 Page 9 BENCHMARK #14 2:l ANALOG MULTIPLEXER Tests the cost/ef ency of a simple analog circuit that operates in a moderately severe envixonment. The switch resistance has a minimum value of 100 ohms and a maximum value of 500 ohms (se
34、e Figure 5 for measurement technique). The switch resistance has to be specified because so many parameters are determined by it. Figure 1 describes the f unc The minimum perform Area including pads Mux Input Range - T vendor must choose a minimum mux input voltage (VML) and a maximu ux input voltag
35、e (VMH). The voltage levels in most of the rest o Over-Voltage Protection (Figure 2) - All parts used for the rest of the measurements must f subjected to this test. Supply Current (Figure 3 Leakage .(Figure 4) Switch Resistance Range Switch Resistance Match Toggle Time (Figure 7) Break-Before-Make
36、Time ( Charge Injection (Figure FeedthEough (Figure 10) Capacitance (Figure 11). ce parameters to be specified are: e measurements are determined by VML and VMH. EIA JESD32-2 86 3234600 0004833 6 JEDEC Standard No. 12-2 Page 10 MOTES TO BEIYCEHABK #14 (1) All .external capacitors and resistors that
37、are shown in the (2) Power supply decoupling capacitors are not shown in the Figures should include the effects of the test fixture. Figures. They may be added as needed. (3) In the Figures, VIL is th and VMH. EIA JESD12-2 8b 3234b00 0004817 7 JEDEC Standard No. 12-2 Page 16 BENCHMARK /I14 FIGURE 6
38、SWITCH RESISTANCE MATCHING - Use the same circuit as in Figure 5. - Use the following definitions: Rfl = ohmmeter.reading when voltage at S is VIL. R1 = ohmmeter reading when voltage at S is VIH. - Matching should be measured with VI set to VML, VMH, and (VML + VMH)/. . . EIA JESDL2-2 86 9 3234600 0
39、004820 3 9 d JEDEC Standard 12-2 Page 17 O BENCHMARK #14 FIGURE f TOGGLE TIME I VML I- EIA JESD32-2 8b = 3234600 0004823 5 JEDEC Standard No. 12-2 Page 18 , “I0 r Pulse BENCHMARK #14 . FIGURE 8 BREAK-BEFORE-MAKE TIME I +“ I Il Li-P I vss A I I EIA JESD12-2 86 m 3234b00 0004822 7 m JEDEC Standard No.
40、 12-2 Page 19 BENCHMARK #14 FIGURE 9 CHARGE INJECTION O Pulse Generator . . Waveform A 10 I + .ns+ I- Waveform S I Apply waveform A to S and measure voltage across C. Apply waveform B to S and measure voltage across Cl. Repoit the measurement-with the largest absolute value. EIA JESD12-2 b W 3234600
41、 0004823 9 W JEDEC Standard No. 12-2 Page 20 Function NCHMARK il14 FIGURE 10 FEEDTHROUGH +v I VDD I0 Generator 1 . Set VI to the following sinewave: Peak-peak voltage = VMH - VML. Frequency = 1 MHz. Measure 20 log 0 VT 1 Repeat for VI connected to Ia and input tp S set to VIH. Report the value corre
42、sponding to maximum feedthrough. EIA JESDL2-2 8b 3234600 0004824 O VIH Set the BENCHMARK #14 . FIGURE 11 CAPACITANCE JEDEC Standard No. 12-2 Page 21 VIL vss I capacitance meter to: Peak-peak voltage = 100 mV Frequency = 1 MHz - Take a capacitance- reading for both switch positions. Report the larger
43、 reading. EIA JESDL2-2 b 3234b00 0004825 2 JEDEC Standard NO. 12-2 Page 22 BENCHMARK #15 COMPARATOR Tests the cost/efficiency of a moderately complex analog function. Small signal response and accuracy are stressed. Figure 1 describes the function. The minimum performance parameters to be specified
44、are: Area including pads Input Range - The vendor must choose a minimum input voltage (VCL) and a maximum input voltage (VCH). The voltage levels in most of the rest of measurements are determined by YCL and VCH. . Supply current Figure 2) . Small signal delay time (Figure 3). Large signal delay tim
45、e (Figure 4). Slew time (Figure 5). Input voltage offset. Input bias current. Input bias current offset. NOTES: (1) All external capacitors and resistors that are shown in s should include the effects of the test (2) Power su decoupling capacitors are not shown in the y may be added as needed. (3) I
46、n the F s the logic iiOs voltage and VOH is at the 0 output. VOL and VOH are EIA JESDL2-2 b W 3234600 0004826 4 W JDEC Standard No. 12-2 Page 23 O BENCHMARK K15 FIGURE 1 COMPARATOR SYMBOL - All bias circuits must be included in the cell. Do not provide an - All offset trimming must be done by the ve
47、ndor. Do not provide extra pin to set supply currents. extra pins for offset trimming. JEDEC Standard No. 12-2 Page 24 BENCHMARK #15 FIGURE 2 SUPPLY CURRENT “CL “CH a +V I I Ammeter I I e The two switches are ganged together, Measure the supply current for both switch pasitions and report the larger
48、 value. EIA JESD12-2 b m 3234600 0004828 m JEDEC Standard No. 12-2 Page 25 . BENCHMARK I15 FIGURE 3 0 LL SIGNAL BELAY TIME Pulse Generator TEST B 0 Repeat Test A and B for V - = VCL, VCH, and (VCL + VCH)/. 0 0 Report the largest td of the six tests. *io% to 90% .time. offset EIA JESDL2-2 b m 3239600
49、 0004829 T m JEDEC Standard No. 12-2 Page 26 BENCHMARK #15 FIGURE 4 LARGE SIGNAL DELAY TIME e O Meagure ti and t2. Repeat the test for v- = VCL, VCH, and (VCL + VcH)/2. Report the largest value of the six measurements. *lo% to 90% time. EIA JESDL2-2 b = 3234b00 0004830 b JEDEC Standard No. 12-2 Page 27 BENCHMARK #15 FIGURE 5 SLEW TIME 0 Pulse Generator The power supply V -_ is used to set the common mode voltage and trim the offset voltage, VOFFSET The input and output waveforms are shown below: I 10ns*, 71 VOFFSET F - t I i I ./-
