1、STD-EIA JESD73-ENGL 1999 I 3234500 Ob22850 301 .I EINJEDEC STANDARD Description of 5 V Bus Switch Devices with TTL- Compatible Control Inputs JESD73 June 1999 ELECTRONIC INDUSTRIES ALLIANCE JEDEC Soiid State Technology Association Electronic Industries Alliance STD=EIA JESD73-ENGL L999 I 3234600 Ob2
2、285L 248 I NOTICE EWJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the EL4 General Counsel. EWJEDEC standards and publications are designed to serve the public inter
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5、obligation whatever to parties adopting the EWJEDEC standards or publications. The information included in EWJEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organiz
6、ation there are procedures whereby an EWJEDEC standard or publication may be further processed and ultimately become an ANSUEIA standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relativ
7、e to the content of this EWJEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.org Published by ELECTRONIC INDUSTRIES ALLIANCE 1999 Engineering Department 2500 Wilson Boulevard
8、 Arlington, VA 22201 -3834 This document may be downloaded free of charge, however EIA retains the copyright on this material, By downloading this file the individual agrees not to charge or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and
9、Publications or call Global Engineering Documents, USA and Canada (1-8OO-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved STD-EIA JESD73-ENGL 1999 I 3234600 Ob22852 384 .I VDD Supply voltage -0.5 to 7.0 V VI dc input voltage, control terminalsQ) -0.5 to 7.0 V vsw dc
10、switch voltage(3) -0.5 to 7.0 V JEDEC Standard No. 73 Page 1 STANDARD FOR DESCRIFTION OF 5 V BUS SWITCH DEVICES WITH TTL-COMPATIBLE CONTROL INPUTS (From JEDEC Board Ballot JCB-99-07, fomulated under the cognizance of the JC-40 Committee on Digital Logic). To provide a set of uniform data sheet param
11、eters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices. 2 Scope This standard covers specifications for a family of 5 V NMOS FET bus switch devices with 5 V T
12、TL compatible control inputs. Not included in this document are device-specific parameters and performance levels that the vendor must also supply for full device description. 3 Terms and defintions (for the purpose of this document) switch device: A semiconductor logic device designed to connect or
13、 disconnect busses or control signals without active drivers in the connection path. connect: A state in a switch device characterized by a minimum series impedance through the designated electrical path. disconnect: A state in a switch device characterized by the high series impedance of the design
14、ated electrical path. 4 Standard specifications 4.1 Absolute maximum conthuous rathgs (2) I Symbol I Parameter I Rating 1 units I IIK I dc input clamp I -50 Id I I bK I dc clamp current, switch terminals I -50 ImA I I =sw I dc continuous channel current I 120 ImA I I TSTG I Storage temperature I -65
15、 to 150 I “C I STD=EIA JESD73-ENGL 1999 M 3234600 0622853 010 9 VIN vsw TA JEDEC Standard No. 73 Page 2 Control input voltage O 5.5 V Switch terminal voltage O 5.5 V Operating free-air temperature -40 85 “C 4 Standard specifications (contd) Symbol Parameter Condition CIN Control input capacitance cs
16、w Switch terminal capacitance Switch disconnected 4.1 Absolute maximum continuous ratings (2)(cont9d) m Unit PF PF NOTE 1 - Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversel
17、y affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Quiescent power supply current DD TTL control inputs high() NOTE 2 - Under transient conditions these ratings may be exceeded as defined elsewhere in this specification. VDD = 5.5 V v, = 3.4 v V
18、sw = GND NOTE 3 - The dc negative voltage ratings may be exceeded if the dc input clamp current ratings are observed. QD 4.2 Recommended operating conditions Dynamic power supply current(2) Vsw = GND Control pin toggling at 10 MHz and 50% duty cycle I Symbol I Parameter IMin IMax !Unit I I vDD I sup
19、ply voltage I 4.5 I 5.5 IV I 43 Capacitance() 4.4 Power supply characteristics I Symbol 1 Description I Test Conditions Quiescent power supply current /IDD I I IlA mA I NOTE 2 - All switch inputs grounded. One control pin toggling. All other control pins at VDD or GND. STD-EIA JESD73-ENGL 1979 I 323
20、4bDD Ob22854 TC7 I Symbol tpLH tPHL tm tm t tPLZ Description Min nP Max Unit Data path propagation delay(*). (*) - ns ns Switch connect delay( 1 Switch disconnect delay() - ns - VpAss Pass voltage drop (VDD - Vo) 1 bS Short circuit current(2)* (4) VIK Clamp diode voltage JEDEC Standard No. 73 Page 3
21、 4.6 dc specifications I Symbol I Parameter Test Conditions /Min Max unit 1 VI, I High-level input voltage I 2.0 I - V I VU. I Low-level input voltage Vsw = VDD VDD = NOTE 5 t Iout = -100 DA V V Switch connect (3) IRON I Quiescent power supply current I IDD 1 VDD = Max., V, = VDD or GND 1- i Switch
22、Terminais Isw=-18 mA I- I V - V Control Terminais, 11=-18 mA I- I Current during switch disconnect IO2 1 1 Controlinputcurrent 1 IOFF 1 Switch terminai leakage() 1- I STDmEIA ESD73-ENGL 1999 II 3234b00 Ob22855 993 I f-2 L JEDEC Standard No. 73 Page 4 4 Standard specifications (contd) 4.6 dc specific
23、ations (contd) NOTE 1 - See the manufacturers data sheet. NOTE 2 - The connect path must be specified. NOTE 3 - Resistance is measured as AV/AI. For Vsw = O V, the resistance is measured while Vom is pulled higher to the designated current level. For VsW = 2.4 V, the resistance is measured while Vom
24、 is pulled lower to the designated current level. NOTE 4 - Not more than one output should be tested at a time. Duration of the test must not exceed one second. This is an optional parameter. NOTE 5 - Optional specification for voltage translation. V, = the recommended voltage for 5 V to 3.3 V volta
25、ge translation. This parameter is characterized but not tested. NOTE 6 - This is an optional parameter. 5 Test circuits and switching waveforms CL = 50 pF or equivalent (includes test setup and probe capacitance). RL = RI = 500 SZ or equivalent RT = Pulse generator termination resistance Pulse gener
26、ator has the following characteristics: $ I 2.5 ns, tf = 5 2.5 ns, PRR I 10 MHz . STD-EIA JESD73-ENGL L999 I 3234600 062265b 82T I JEDEC Standard No. 73 Page 5 5 Test Circuits and Switching Waveforms PROPAGATION DELAY MEASUREMENTS CONNECT DELAY MEASUREMENTS -1.5V ov - Control Input - I I - - -VOH -
27、1.5v - Switch Output (Switch Input = 3.0 V) 1 -i- - - - - - -VOH - 1.5V - - Switch Output (Switch Input = GND) -VOL DISCONNECT DELAY MEASUREMENTS -3.0 V -1.5V ov - - Control Input - I I - - -VOH tPLZ i, VOL + 0.3 V - Switch Output (Switch Input = GND) 1 -i- - - - - - - VOL -VOH Switch Output - VOH - 0.3 v - - -VOL (Switch Input = 3.0 V) NOTE - Reference to other applicable JEDEC Standards and Publications
