1、EIA JESDB-4 93 Reproduced By GLOBAL ENGINEERING DOCUMENTS With Th* Permission o EIA Under Royalty Agreement RZ 3234600 0550491 261 t I JEDEC STANDARD Center-Tap-Terminated (CTT) Low-Level, High-speed Interface Standard for Digital Integrated Circuits JESDS-4 NOVEhIBER 1993 ELECTRONIC INDUSTRIES ASSO
2、CIATION ENGINEERING DEPARTMENT COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESDB-4 93 3231.1600 0550492 LT8 NOTICE JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level a
3、nd subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purch
4、aser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such stand
5、ards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally, JEDEC Standards and Publications are adopted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action
6、, JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principall
7、y from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately became an EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard should
8、be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Pennsylvania Ave., N.W., Washington, D.C. 20006. Published by ELECTRONIC INDUSTRIES ASSOCIATION 1993 Eng n eeri ng Department 2001 Pennsylvania Ave., N.W. Washington, D.C. 20006 PRICE: Please refer to the current Catalog of EIA
9、& JEDEC STANDARDS & ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-71 79) International (303-397-7956) Printed in U.S.A. All rights reserved COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESDB-4 93 W 3234600 0550493 034
10、 m PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the EL4 and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement with the EIA. For information, contact: EM Engineering Publicat
11、ions Office 2001 Pennsylvania Ave., N.W. Washington, D.C. 20006 (202)457-4963 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESDB-4 93 D 3234b00 0554539 628 JEDEC STANDARD NO. 8-4 Page 1 CENTER-TAP-TERMINATED (CTT) LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR D
12、IGITAL INTEGRATED CIRCUITS (From JEDEC Council Ballot, JCB-93-51, formulated under the cognizance of the JC-16 Committee on Electrical Interface and Power Supply Standards for Electronic Components) 1. SCOPE This standard defines the dc input and output specifications for a low-level, high-speed int
13、erface for integrated circuits that can be a suDer-set of LVCMOS and LVTTL. 1.1 Standard Specifications As a super-set, CT receivers are compatible with standard LVCMOS and LVTTL drivers. CTT drivers, when unterminated, perform in a manner compatible with dc and ac specifications for LVCMOS or LVTL.
14、 The interface standards for terminated use are defined in Table 1. The input specifications imply an input comparator stage operating about the specified reference voltage of 1.5 V t 10% which also serves as the termination supply as output drive is symmetrical about this level. 0 1.1.1 Terminated
15、Case In the terminated case the minimum output swing is defined by the termination impedance. The output drive is current limited to achieve this and the swing is defined for a 50 ohm termination. A block diagram is appended in Figure 1 for reference only. 1.1.2 Unterminated Case In unterminated ope
16、ration, additional drive may be provided until the output level passes through the receiver threshold to allow circuit switching speed that matches regular rail-to-rail swing drivers. (Not necessary for output slew rates 8 V/ns per pF of load capacitance). For reference information only, a CMOS circ
17、uit operating in this fashion is appended. (See Figure 2.) COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESDB-4 93 3234600 0554540 34T T- Reproduced By GLOBAL a ENGINEERING DOCUMENTS mT With The Permission 01 EIA -. - Under Royalty Agreement JEDEC STANDARD NO.
18、 8-4 Page 2 2. APPLICATION NOTES 2.1 Applicability to Alternative Voltage Level Systems CTT-compatible devices are expected to be used in systems with several VD, power supply voltages including VDD = 3.3 V and 2.X volts. Many generations of devices and power supply standards can most readily be acc
19、ommodated by regarding the center level, Vn/VREF, as ground with all signals referenced relative to ground. For 2.X parts, the 1.5V reference can be maintained using conventional ground and positive reference/termination levels. In general, no translation circuits will be needed to interface CT circ
20、uits to standard LVTTL/CMOS devices. Table 1 CTT Standard Specifications* * These min and max values for VOL and V, are specified for nominal power supplies and temperature as they impact power consumption and not functionality. * CTT has not been patented nor is any patent protection being sought.
21、COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesJEDEC STANDARD No. 8-4 Page 3 DRTR OUT O 8 D- DRTQ OUT zo -f J TRISTRTE CONTROL I DRIVER CONTROL a DQTR IN - CTT DRIVER CTT RECEIVER Figure 1 (For Reference Only) 1“ I I I 1 (ENRBLE 1 Figure 2 (For Reference Only) COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESDB-4 73 W 3234600 0550545 262 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services
