IEC 60191-6-17-2011 Mechanical standardization of semiconductor devices - Part 6-17 General rules for the preparation of outline drawings of surface mounted semiconductor device pa.pdf

1、 IEC 60191-6-17 Edition 1.0 2011-01 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardization of semiconductor devices Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for stacked packages Fine-pitch ball grid

2、 array and fine-pitch land grid array (P-PFBGA and P-PFLGA) Normalisation mcanique des dispositifs semiconducteurs Partie 6-17: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs montage en surface Guide de conception pour les botiers empils Botiers matriciels

3、 billes et pas fins et botiers matriciels zone de contact plate et pas fins (P-PFBGA et P-PFLGA) IEC 60191-6-17:2011 THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2011 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utili

4、zed in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either IEC or IECs member National Committee in the country of the requester. If you have any questions about IEC copyright or have an enquiry about obtaining additiona

5、l rights to this publication, please contact the address below or your local IEC member National Committee for further information. Droits de reproduction rservs. Sauf indication contraire, aucune partie de cette publication ne peut tre reproduite ni utilise sous quelque forme que ce soit et par auc

6、un procd, lectronique ou mcanique, y compris la photocopie et les microfilms, sans laccord crit de la CEI ou du Comit national de la CEI du pays du demandeur. Si vous avez des questions sur le copyright de la CEI ou si vous dsirez obtenir des droits supplmentaires sur cette publication, utilisez les

7、 coordonnes ci-aprs ou contactez le Comit national de la CEI de votre pays de rsidence. IEC Central Office 3, rue de Varemb CH-1211 Geneva 20 Switzerland Email: inmailiec.ch Web: www.iec.ch About the IEC The International Electrotechnical Commission (IEC) is the leading global organization that prep

8、ares and publishes International Standards for all electrical, electronic and related technologies. About IEC publications The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the latest edition, a corrigenda or an amendment might have be

9、en published. Catalogue of IEC publications: www.iec.ch/searchpub The IEC on-line Catalogue enables you to search by a variety of criteria (reference number, text, technical committee,). It also gives information on projects, withdrawn and replaced publications. IEC Just Published: www.iec.ch/online

10、_news/justpub Stay up to date on all new IEC publications. Just Published details twice a month all new publications released. Available on-line and also by email. Electropedia: www.electropedia.org The worlds leading online dictionary of electronic and electrical terms containing more than 20 000 t

11、erms and definitions in English and French, with equivalent terms in additional languages. Also known as the International Electrotechnical Vocabulary online. Customer Service Centre: www.iec.ch/webstore/custserv If you wish to give us your feedback on this publication or need further assistance, pl

12、ease visit the Customer Service Centre FAQ or contact us: Email: csciec.ch Tel.: +41 22 919 02 11 Fax: +41 22 919 03 00 A propos de la CEI La Commission Electrotechnique Internationale (CEI) est la premire organisation mondiale qui labore et publie des normes internationales pour tout ce qui a trait

13、 llectricit, llectronique et aux technologies apparentes. A propos des publications CEI Le contenu technique des publications de la CEI est constamment revu. Veuillez vous assurer que vous possdez ldition la plus rcente, un corrigendum ou amendement peut avoir t publi. Catalogue des publications de

14、la CEI: www.iec.ch/searchpub/cur_fut-f.htm Le Catalogue en-ligne de la CEI vous permet deffectuer des recherches en utilisant diffrents critres (numro de rfrence, texte, comit dtudes,). Il donne aussi des informations sur les projets et les publications retires ou remplaces. Just Published CEI: www.

15、iec.ch/online_news/justpub Restez inform sur les nouvelles publications de la CEI. Just Published dtaille deux fois par mois les nouvelles publications parues. Disponible en-ligne et aussi par email. Electropedia: www.electropedia.org Le premier dictionnaire en ligne au monde de termes lectroniques

16、et lectriques. Il contient plus de 20 000 termes et dfinitions en anglais et en franais, ainsi que les termes quivalents dans les langues additionnelles. Egalement appel Vocabulaire Electrotechnique International en ligne. Service Clients: www.iec.ch/webstore/custserv/custserv_entry-f.htm Si vous ds

17、irez nous donner des commentaires sur cette publication ou si vous avez des questions, visitez le FAQ du Service clients ou contactez-nous: Email: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 60191-6-17 Edition 1.0 2011-01 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardi

18、zation of semiconductor devices Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) Normalisation mcanique des dispositifs s

19、emiconducteurs Partie 6-17: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs montage en surface Guide de conception pour les botiers empils Botiers matriciels billes et pas fins et botiers matriciels zone de contact plate et pas fins (P-PFBGA et P-PFLGA) INT

20、ERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE U ICS 31.080.01 PRICE CODE CODE PRIX ISBN 978-2-88912-331-5 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale 2 60191-6-17 IEC:2011 CONT

21、ENTS FOREWORD . 3 INTRODUCTION . 5 1 Scope . 6 2 Normative references . 6 3 Definitions 6 4 Terminal position numbering 7 5 Drawings 8 6 Dimensions 16 6.1 Group 1 . 16 6.2 Group 2 . 21 7 Dimension table . 27 Figure 1 Individual stackable package, P-FBGA (cavity-up) . 8 Figure 2 Individual stackable

22、package, P-FBGA (cavity-down) . 9 Figure 3 Individual stackable package, P-FLGA (cavity-up) . 10 Figure 4 Stacked package outline, P-PFBGA (cavity-up BGA and cavity-up BGA) . 11 Figure 5 Stacked package outline, P-PFBGA (cavity-down BGA and cavity-down BGA) 12 Figure 6 Stacked package outline, P-PFB

23、GA (cavity-down BGA + cavity-up LGA） . 13 Figure 7 Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA) 14 Figure 8 Functional gauge . 15 Figure 9 Pattern of terminal position area 15 Table 1 Dimensions, Group 1 . 16 Table 2 Dimensions Group 2 21 Table 3 Combination of D, E, M D , and M

24、E , e = 0.80mm pitch FBGA and FLGA . 22 Table 4 Combination of D, E, M D , and M E , e = 0,65mm pitch FBGA and FLGA . 23 Table 5 Combination of D, E, M D , and M E , e = 0,50mm pitch FBGA and FLGA . 24 Table 6 Combination of D, E, M D , and M E , e = 0,40mm pitch FBGA an FLGA . 25 Table 7 Combinatio

25、n of D, E, M D , and M E , e = 0,30mm pitch FLGA. 26 Table 8 Dimension table 27 60191-6-17 IEC:2011 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor devi

26、ce packages Design guide for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC Natio

27、nal Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Public

28、ly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governme

29、ntal organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on t

30、echnical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted b

31、y IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international un

32、iformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.

33、5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any services carried out by independent certification bodies. 6) All users should en

34、sure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of

35、 any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the r

36、eferenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. In

37、ternational Standard IEC 60191-6-17 has been prepared by subcommittee 47D: Mechanical standardization for semiconductor devices, of IEC technical committee 47: Semiconductor devices. The text of this standard is based on the following documents: FDIS Report on voting 47D/785/FDIS 47D/793/RVD Full in

38、formation on the voting for the approval of this standard can be found in the report on voting indicated in the above table. 4 60191-6-17 IEC:2011 This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all the parts in the IEC 60191 series, under the general t

39、itle Mechanical standardization of semiconductor devices, can be found on the IEC website. The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific pu

40、blication. At this date, the publication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. 60191-6-17 IEC:2011 5 INTRODUCTION The trend toward downsizing and higher density of portable electronic devices has driven LSI packages into smaller and higher density configurations.

41、 The market demand of higher density has led to the development of the package stacking technology that enabled miniaturization and higher functionality. The objective of this design guide is to standardize outlines and to get interchangeability of individual stackable packages. 6 60191-6-17 IEC:201

42、1 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) 1 Scope This part

43、of IEC 60191 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited app

44、lies. For undated references, the latest edition of the referenced document applies. IEC 60191-6, Mechanical standardization of semiconductor devices Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device package IEC 60191-6-5, Mechanical standardizatio

45、n of semiconductor devices Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA) 3 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 60191-6 a

46、nd the following apply. 3.1 individual stackable package package with an array of metallic balls or lands on the underside of the package for the purpose of surface-mount on a printed circuit board and an array of footprints (lands) on the upper side of the package for stacking packages NOTE The ind

47、ividual stackable cavity-up FLGA package is a part of this specification on the premise of stacking a cavity-down FBGA with cavity-up FLGA. 3.2 stacked package assembly of multiple individual stackable packages in a stacked configuration NOTE The top package can be a standard FBGA specified in IEC 6

48、0191-6-5 without any footprints on the upper side of the package. The stand-off height of this standard package, however, shall follow this design guide. 3.3 mould cap height (A 2 ) height of the mould cap which contains wire-bonded die or of the exposed flip chip-bonded die with respect to the uppe

49、r substrate surface of the package 60191-6-17 IEC:2011 7 3.4 distance between the mould cap edge and innermost balls (F) distance between the mould cap edge of the lower package and the innermost terminals of the upper package of the stacked package 3.5 upper side land grid pitch (e 1 ) grid pitch of the footprints (lands) on the