1、 IEC 60191-6-17 Edition 1.0 2011-01 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardization of semiconductor devices Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for stacked packages Fine-pitch ball grid
2、 array and fine-pitch land grid array (P-PFBGA and P-PFLGA) Normalisation mcanique des dispositifs semiconducteurs Partie 6-17: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs montage en surface Guide de conception pour les botiers empils Botiers matriciels
3、 billes et pas fins et botiers matriciels zone de contact plate et pas fins (P-PFBGA et P-PFLGA) IEC 60191-6-17:2011 THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2011 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utili
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17、irez nous donner des commentaires sur cette publication ou si vous avez des questions, visitez le FAQ du Service clients ou contactez-nous: Email: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 60191-6-17 Edition 1.0 2011-01 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardi
18、zation of semiconductor devices Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) Normalisation mcanique des dispositifs s
19、emiconducteurs Partie 6-17: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs montage en surface Guide de conception pour les botiers empils Botiers matriciels billes et pas fins et botiers matriciels zone de contact plate et pas fins (P-PFBGA et P-PFLGA) INT
20、ERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE U ICS 31.080.01 PRICE CODE CODE PRIX ISBN 978-2-88912-331-5 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale 2 60191-6-17 IEC:2011 CONT
21、ENTS FOREWORD . 3 INTRODUCTION . 5 1 Scope . 6 2 Normative references . 6 3 Definitions 6 4 Terminal position numbering 7 5 Drawings 8 6 Dimensions 16 6.1 Group 1 . 16 6.2 Group 2 . 21 7 Dimension table . 27 Figure 1 Individual stackable package, P-FBGA (cavity-up) . 8 Figure 2 Individual stackable
22、package, P-FBGA (cavity-down) . 9 Figure 3 Individual stackable package, P-FLGA (cavity-up) . 10 Figure 4 Stacked package outline, P-PFBGA (cavity-up BGA and cavity-up BGA) . 11 Figure 5 Stacked package outline, P-PFBGA (cavity-down BGA and cavity-down BGA) 12 Figure 6 Stacked package outline, P-PFB
23、GA (cavity-down BGA + cavity-up LGA） . 13 Figure 7 Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA) 14 Figure 8 Functional gauge . 15 Figure 9 Pattern of terminal position area 15 Table 1 Dimensions, Group 1 . 16 Table 2 Dimensions Group 2 21 Table 3 Combination of D, E, M D , and M
24、E , e = 0.80mm pitch FBGA and FLGA . 22 Table 4 Combination of D, E, M D , and M E , e = 0,65mm pitch FBGA and FLGA . 23 Table 5 Combination of D, E, M D , and M E , e = 0,50mm pitch FBGA and FLGA . 24 Table 6 Combination of D, E, M D , and M E , e = 0,40mm pitch FBGA an FLGA . 25 Table 7 Combinatio
25、n of D, E, M D , and M E , e = 0,30mm pitch FLGA. 26 Table 8 Dimension table 27 60191-6-17 IEC:2011 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor devi
26、ce packages Design guide for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC Natio
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37、ternational Standard IEC 60191-6-17 has been prepared by subcommittee 47D: Mechanical standardization for semiconductor devices, of IEC technical committee 47: Semiconductor devices. The text of this standard is based on the following documents: FDIS Report on voting 47D/785/FDIS 47D/793/RVD Full in
38、formation on the voting for the approval of this standard can be found in the report on voting indicated in the above table. 4 60191-6-17 IEC:2011 This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all the parts in the IEC 60191 series, under the general t
39、itle Mechanical standardization of semiconductor devices, can be found on the IEC website. The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific pu
40、blication. At this date, the publication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. 60191-6-17 IEC:2011 5 INTRODUCTION The trend toward downsizing and higher density of portable electronic devices has driven LSI packages into smaller and higher density configurations.
41、 The market demand of higher density has led to the development of the package stacking technology that enabled miniaturization and higher functionality. The objective of this design guide is to standardize outlines and to get interchangeability of individual stackable packages. 6 60191-6-17 IEC:201
42、1 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) 1 Scope This part
43、of IEC 60191 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited app
44、lies. For undated references, the latest edition of the referenced document applies. IEC 60191-6, Mechanical standardization of semiconductor devices Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device package IEC 60191-6-5, Mechanical standardizatio
45、n of semiconductor devices Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA) 3 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 60191-6 a
46、nd the following apply. 3.1 individual stackable package package with an array of metallic balls or lands on the underside of the package for the purpose of surface-mount on a printed circuit board and an array of footprints (lands) on the upper side of the package for stacking packages NOTE The ind
47、ividual stackable cavity-up FLGA package is a part of this specification on the premise of stacking a cavity-down FBGA with cavity-up FLGA. 3.2 stacked package assembly of multiple individual stackable packages in a stacked configuration NOTE The top package can be a standard FBGA specified in IEC 6
48、0191-6-5 without any footprints on the upper side of the package. The stand-off height of this standard package, however, shall follow this design guide. 3.3 mould cap height (A 2 ) height of the mould cap which contains wire-bonded die or of the exposed flip chip-bonded die with respect to the uppe
49、r substrate surface of the package 60191-6-17 IEC:2011 7 3.4 distance between the mould cap edge and innermost balls (F) distance between the mould cap edge of the lower package and the innermost terminals of the upper package of the stacked package 3.5 upper side land grid pitch (e 1 ) grid pitch of the footprints (lands) on the
