A Configurable Radiation Tolerant Dual-Ported Static RAM .ppt

1、“A Configurable Radiation Tolerant Dual-Ported Static RAM macro, designed in a 0.25 m CMOS technology for applications in the LHC environment.”,8th Workshop on Electronics for LHC Experiments 9-13 Sept. 2002, Colmar, FranceK. Kloukinas, G. Magazzu, A. Marchioro CERN EP division, 1211 Geneva 23, Swit

2、zerland,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,2,Overview,Motive of Work Description of the macro-cell design Experimental Results Conclusions,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,3,Motive of Work,Several Front-End ASICs for the LHC detectors are using the CERN DSM Design Kit in 0.25 m commerc

3、ial CMOS technology. Many ASICs require the use of rather large memories in Readout Pipelines, Readout Buffers and FIFOs. CERN DSM Design Kit lacks design automation tools for generating customized SRAM blocks.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,4,Proposed Design,Built an SRAM macro-cell that

4、can be configured in terms of word counts and bit organization by means of simple floorplanning procedures. Initially designed for the needs of the “Kchip” Front-End ASIC used in the CMS ECAL Preshower detector.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,5,CERN-SRAM specifications,Scalable Design Conf

5、igurable Bit organization (n x 9-bit). Configurable Memory Size (128 4Kwords). Synchronous Dual-Port Operation Permits Read/Write operations on the same clock cycle. Typical Operating Frequency: 40 MHz. Low Power Design Full Static Operation. Divided Wordline Decoding. Radiation Tolerant Design,Sept

6、 12, 2002,KLOUKINAS Kostas EP/CME-PS,6,Memory Cell,To minimize the macro-cell area a Single Port memory cell is used based on a conventional cross-coupled inverter scheme. Gain in Memory Cell Layout Area = 18%,Dual Port SRAM Cell,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,7,Memory Cell Design,Single P

7、ort memory cell Interconnect: 3 metal layers1st for local interconnects2nd for vertical bitlines and power lines3rd for horizontal wordlines Memory Cell Area: 47.152 m2,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,8,SRAM Block Diagram,Dual-port functionality is realized with a time sharing access mechan

8、ism.Registered Inputs Latched Outputs,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,9,SRAM Interface Timing,Clk,WA,R,Din,Dout,WRITE,READ,READ/WRITE,tS,tH,W,RA,tS,tH,tacc,1,2,3,4,5,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,10,SRAM macro-cell Design,Address Decoding,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,

9、11,Address Mux Register,Leaf cell is based on the D-F/F and the 2-input Mux standard cells found in the CERN DSM Design Kit. True & Complementary output with balanced timing. Easily sizeable by abutting the necessary number of leaf cells.,Leaf Cell,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,12,Row Dec

10、oder,WL,Decoder: 7 to 128 Hardwire-configured. Pre-routed layout block. Dynamic NAND-type. Speed, Area, Power advantages over the static NAND-type. Latched output.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,13,Column Decoder,Static NAND-type implementation Column decoding is one of the last actions to

11、 be performed in the read sequence. It can be executed in parallel with other functions, and can be performed as soon as address is available. Its propagation delay does not add to the overall memory access time.Size Configurable Make use of Design kit standard cells. Decoding function is via-hole p

12、rogrammable.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,14,Divided Wordline Decoding,Reduced Power Consumption. The non accessed portions of the memory remain in the precharge state. Improved Wordline Selection Time. Since the RC delay in each divided wordline is small due to its short length.,Sept 12

13、, 2002,KLOUKINAS Kostas EP/CME-PS,15,Divided Wordline Decoding,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,16,SRAM macro-cell Design,Data Path,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,17,Data Input Output Ports,Data Input Register Leaf cell is based on the D-F/F standard cell from CERN DSM Design Kit.

14、True & Complementary output with balanced timing. Data Output Latch Leaf cell is based on the Latch standard cell from CERN DSM Design Kit. Easily sizeable by abutting the necessary number of leaf cells.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,18,SRAM Data Path,Bit Line,Bit Line,Word Line,Data in,W

15、rite enable,BLPC,Data out,Latch,Clk,Read Logic,Write Drivers,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,19,Read Logic,Substitution of the conventional sense amplifier with an asymmetric inverter. Reduced Power Consumption Stable operation al low power supply voltages. Acceptable performance for target

16、 applications. Easy to design.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,20,Replica Techniques,Scalability Wordline select time depends on the size of the memory. Dummy Wordline with replica memory cells to track the wordline charge-discharge time. Bitline Timing Dummy Bitlines to mimic the delay of

17、the bitline path over all conditions.,SRAM Array,128 rows,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,21,Replica Techniques,Bit Line,Bit Line,Local Word Line,Data in,WEN,Data out,Row Decoder,LWLdummy,BL0,Block Select,Global Word Line,Dummy Bit Lines,BL,BL,Dummy Word Line,Latch,Sept 12, 2002,KLOUKINAS K

18、ostas EP/CME-PS,22,Timing Logic,Timing Logic,WLpc,BLpc,REN,WEN,Latch,Clk,R,W,WLdummy,BL0,SRAM Interface,Memory Cell Array,Memory Cell Array,Data Ouput Latch,Data Input Register,Address Mux Register,Clk,Clk,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,23,Timing Logic,Asynchronous internal timing of contr

19、ol signals. Static operation. Hand-shaking and transition detection to realize internal timing loops. Timing loops are initiated by the system clock and terminated upon completion of the operation. All control signals are forced back to their initial state to prepare for subsequent tasks. During sta

20、ndby periods, bitlines and wordlines precharge-evaluate cycles are not initiated, thus keeping the Power Consumption to a minimum.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,24,Operation and Timing,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,25,Cell Library,Row Decoder,WordLine Buffers,SRAM column, 128 x

21、 9bits,Column Decoder,Timing logic,Output Data Latche,Data Input Register,Address Mux Register,Block Pre-Decoder,(50.4 m x 1086.2 m),Size Configurable,Fixed Layout,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,26,Floorplanning,Block,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,27,CAD Tools Support,Digital Si

22、mulation,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,28,CAD Tools Support,Logic Synthesis,Logic Synthesis Tool SYNOPSYS,SRAM timing,Design Kit .lib file,Combined .lib file,Combined .db file,compilation,Template,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,29,CAD Tools Support,Place & Route,SRAM timing,Plac

23、e & Route Tool Silicon Ensemble,Design Kit TLF file,Combined TLF file,Layout view,Abstract view,Combined CTLF file,compilation,LEF file,Template,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,30,Experimental Results,To prove the concept of the SRAM macro-cell scalability and to evaluate the performance of

24、 the proposed design we have fabricated two test chips: a 1Kwords X 9bits and a 4Kwords X 9bits. Both chips were tested and found functional.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,31,Submitted SRAM Chips,1st Prototype Design: CERN_SRAM_1K Configuration: 1K x 9 bit Size: 560m x 1,300m Area: 0.73mm

25、2 Density: 12.6Kbit/mm2,The Memory consists of2 Blocks of 512 x 9bits. Each Block is composed by 4 Columns of 128 X 9bits.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,32,Submitted SRAM Chips,2nd Prototype Design: CERN_SRAM_4K Configuration: 4K x 9 bit Size: 1,850m x 1,300m Area: 2.4mm2 Density: 15.4Kbi

26、t/mm2,The Memory consists of8 Blocks of 512 x 9bits. Each Block is composed by 4 Columns of 128 X 9bits.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,33,CERN SRAM test results,Functional tests Max operating frequency: Simultaneous Read/Write operations: 70MHz 2.5V Read access time: 7.5ns 2.5V Power diss

27、ipation: 15W / MHz 2.5V for simultaneous Read/Write operations on the same clock cycle (0.60mW 40MHz). Tests for process variations: Differences in the access time 1ns for: -3, 1.5, typ, +1.5, +3,Test chip: 4Kx9bit,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,34,Performance Tests,Test Chip: 4Kword X 9bi

28、ts Operation Frequency: 50MHz Power Supply: 2.5Volts Read Access Time: 7.5nsec,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,35,Performance Tests,Test Chip: 4Kword X 9bits Power Supply: 2.0 - 2.7Volts Operation Frequency: 50MHz Test Patterns: All 1s and all 0s Checkerboard Marching 1s Marching 0s,Pass,Se

29、pt 12, 2002,KLOUKINAS Kostas EP/CME-PS,36,Power dissipation,Power dissipation of macro-cell.Test chip: 4Kwords x 9bits,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,37,Irradiation Tests,Ionizing Total Dose Conditions Source: X-rays. Step Irradiation: 1Mrad, 5Mrad, 10Mrad. Constant dose rate: 21.2 Krad/mi

30、n. Annealing: 24h 25 oC. Under bias, in Standby mode during irradiation & annealing. Results No increase in power dissipation. No measurable degradation in performance. Single Event Upset: Under preparation,Test chip: 4Kwords x 9bit,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,38,CERN SRAM popularity !,

31、ATLAS MCC chipMemory configuration: 128 x 27bitDetector: ATLAS PIXELLab: INFN GenovaALICE AMBRA chipMemory configuration: 16K X 9 bitsDetector: ALICE Silicon Drift Det.Lab: INFN TorinoALICE CARLOS chipMemory configuration: 256 X 9 bitsDetector: ALICE Silicon Drift Det.Lab: INFN BolognaLHCb SYNC chip

32、Memory configuration: 256 X 9 bitsDetector: LHCb muon systemLab: INFN Cagliary,ATLAS SCAC chipMemory configuration: 128 x 18bitDetector: ATLAS trackerLab: NEVIS LabsATLAS DTMROC chipMemory configuration: 128 x 153 bitsDetector: ATLAS TRTLab: CERNCMS KchipMemory configuration: 2K x 18 bits 128 x 18 b

33、itsDetector: CMS PreshowerLab: CERN,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,39,Design Support,Delivery of SRAM design library,Half a day “design course” CERN,Designer configures his macrocell,Review the macrocell design,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,40,Conclusions,Design Status Design me

34、ets target specifications. Macrocell has been successfully used in a number of ASIC designs. Future Plans No further development is foreseen.Design Support Contact Person: Kostas.KloukinasCERN.ch Information on the Web http:/home.cern.ch/kkloukin,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,41,Floorplanning,