A Configurable Radiation Tolerant Dual-Ported Static RAM .ppt
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1、“A Configurable Radiation Tolerant Dual-Ported Static RAM macro, designed in a 0.25 m CMOS technology for applications in the LHC environment.”,8th Workshop on Electronics for LHC Experiments 9-13 Sept. 2002, Colmar, FranceK. Kloukinas, G. Magazzu, A. Marchioro CERN EP division, 1211 Geneva 23, Swit
2、zerland,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,2,Overview,Motive of Work Description of the macro-cell design Experimental Results Conclusions,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,3,Motive of Work,Several Front-End ASICs for the LHC detectors are using the CERN DSM Design Kit in 0.25 m commerc
3、ial CMOS technology. Many ASICs require the use of rather large memories in Readout Pipelines, Readout Buffers and FIFOs. CERN DSM Design Kit lacks design automation tools for generating customized SRAM blocks.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,4,Proposed Design,Built an SRAM macro-cell that
4、can be configured in terms of word counts and bit organization by means of simple floorplanning procedures. Initially designed for the needs of the “Kchip” Front-End ASIC used in the CMS ECAL Preshower detector.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,5,CERN-SRAM specifications,Scalable Design Conf
5、igurable Bit organization (n x 9-bit). Configurable Memory Size (128 4Kwords). Synchronous Dual-Port Operation Permits Read/Write operations on the same clock cycle. Typical Operating Frequency: 40 MHz. Low Power Design Full Static Operation. Divided Wordline Decoding. Radiation Tolerant Design,Sept
6、 12, 2002,KLOUKINAS Kostas EP/CME-PS,6,Memory Cell,To minimize the macro-cell area a Single Port memory cell is used based on a conventional cross-coupled inverter scheme. Gain in Memory Cell Layout Area = 18%,Dual Port SRAM Cell,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,7,Memory Cell Design,Single P
7、ort memory cell Interconnect: 3 metal layers1st for local interconnects2nd for vertical bitlines and power lines3rd for horizontal wordlines Memory Cell Area: 47.152 m2,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,8,SRAM Block Diagram,Dual-port functionality is realized with a time sharing access mechan
8、ism.Registered Inputs Latched Outputs,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,9,SRAM Interface Timing,Clk,WA,R,Din,Dout,WRITE,READ,READ/WRITE,tS,tH,W,RA,tS,tH,tacc,1,2,3,4,5,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,10,SRAM macro-cell Design,Address Decoding,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,
9、11,Address Mux Register,Leaf cell is based on the D-F/F and the 2-input Mux standard cells found in the CERN DSM Design Kit. True & Complementary output with balanced timing. Easily sizeable by abutting the necessary number of leaf cells.,Leaf Cell,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,12,Row Dec
10、oder,WL,Decoder: 7 to 128 Hardwire-configured. Pre-routed layout block. Dynamic NAND-type. Speed, Area, Power advantages over the static NAND-type. Latched output.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,13,Column Decoder,Static NAND-type implementation Column decoding is one of the last actions to
11、 be performed in the read sequence. It can be executed in parallel with other functions, and can be performed as soon as address is available. Its propagation delay does not add to the overall memory access time.Size Configurable Make use of Design kit standard cells. Decoding function is via-hole p
12、rogrammable.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,14,Divided Wordline Decoding,Reduced Power Consumption. The non accessed portions of the memory remain in the precharge state. Improved Wordline Selection Time. Since the RC delay in each divided wordline is small due to its short length.,Sept 12
13、, 2002,KLOUKINAS Kostas EP/CME-PS,15,Divided Wordline Decoding,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,16,SRAM macro-cell Design,Data Path,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,17,Data Input Output Ports,Data Input Register Leaf cell is based on the D-F/F standard cell from CERN DSM Design Kit.
14、True & Complementary output with balanced timing. Data Output Latch Leaf cell is based on the Latch standard cell from CERN DSM Design Kit. Easily sizeable by abutting the necessary number of leaf cells.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,18,SRAM Data Path,Bit Line,Bit Line,Word Line,Data in,W
15、rite enable,BLPC,Data out,Latch,Clk,Read Logic,Write Drivers,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,19,Read Logic,Substitution of the conventional sense amplifier with an asymmetric inverter. Reduced Power Consumption Stable operation al low power supply voltages. Acceptable performance for target
16、 applications. Easy to design.,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,20,Replica Techniques,Scalability Wordline select time depends on the size of the memory. Dummy Wordline with replica memory cells to track the wordline charge-discharge time. Bitline Timing Dummy Bitlines to mimic the delay of
17、the bitline path over all conditions.,SRAM Array,128 rows,Sept 12, 2002,KLOUKINAS Kostas EP/CME-PS,21,Replica Techniques,Bit Line,Bit Line,Local Word Line,Data in,WEN,Data out,Row Decoder,LWLdummy,BL0,Block Select,Global Word Line,Dummy Bit Lines,BL,BL,Dummy Word Line,Latch,Sept 12, 2002,KLOUKINAS K
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