ImageVerifierCode 换一换
格式:PDF , 页数:15 ,大小:103.54KB ,
资源ID:700013      下载积分:10000 积分
快捷下载
登录下载
邮箱/手机:
温馨提示:
如需开发票,请勿充值!快捷下载时,用户名和密码都是您填写的邮箱或者手机号,方便查询和重复下载(系统自动生成)。
如填写123,账号就是123,密码也是123。
特别说明:
请自助下载,系统不会自动发送文件的哦; 如果您已付费,想二次下载,请登录后访问:我的下载记录
支付方式: 支付宝扫码支付 微信扫码支付   
注意:如需开发票,请勿充值!
验证码:   换一换

加入VIP,免费下载
 

温馨提示:由于个人手机设置不同,如果发现不能下载,请复制以下地址【http://www.mydoc123.com/d-700013.html】到电脑端继续下载(重复下载不扣费)。

已注册用户请登录:
账号:
密码:
验证码:   换一换
  忘记密码?
三方登录: 微信登录  

下载须知

1: 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。
2: 试题试卷类文档,如果标题没有明确说明有答案则都视为没有答案,请知晓。
3: 文件的所有权益归上传用户所有。
4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
5. 本站仅提供交流平台,并不能对任何下载内容负责。
6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。

版权提示 | 免责声明

本文(DLA SMD-5962-91611 REV B-2009 MICROCIRCUIT DIGITAL ADVANCED CMOS 8-BIT D FLIP-FLOP POSITIVE EDGE-TRIGGERED WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf)为本站会员(appealoxygen216)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-91611 REV B-2009 MICROCIRCUIT DIGITAL ADVANCED CMOS 8-BIT D FLIP-FLOP POSITIVE EDGE-TRIGGERED WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Make correction to figures 2 and 4. Update boilerplate jak. 00-07-18 Monica L. Poelking B Update the boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 09-03-24 Thomas M. Hess REV SHET REV SHET REV STATUS REV B B B B B B B B

2、B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Marcia B. Kelleher CHECKED BY Thomas J. Ricciuti DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Michael A. Frye STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR U

3、SE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-11-01 MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 8-BIT D FLIP-FLOP, POSITIVE EDGE-TRIGGERED WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-91

4、611 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E200-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91611 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR

5、97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When a

6、vailable, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91611 01 M K A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead

7、finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels

8、and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACT825 8-bit D flip-flop, positive edge-triggered with three-state outputs, T

9、TL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B micro

10、circuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat pa

11、ck L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted

12、 without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91611 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.

13、5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Input clamp diode current 20 mA Output clamp diode current 20 mA DC output current. 50 mA DC VCCor GND current (per pin) . 50 mA Maximum power dissipation (PD) . 500 mW Storage temperature range (TSTG) . -65C to +15

14、0C Lead temperature (soldering, 10 seconds). +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 3/ 1.4 Recommended operating conditions. 1/ 2/ 4/ Supply voltage range (VCC) 4.5 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VCCOutput voltage

15、range (VOUT). +0.0 V dc to VCCCase operating temperature range (TC). -55C to +125C Input rise or fall times (VCC= 4.5 V to 5.5 V) 0 to 8 ns/V Minimum setup time, data (Dn) to clock (CP) (ts1): TC= +25C, VCC = 4.5 V. 3.5 ns TC= -55C and +125C, VCC= 4.5 V 4.0 ns Minimum setup time, enable (EN) to (CP)

16、 (ts2): TC= +25C, VCC = 4.5 V. 3.5 ns TC= -55C and +125C, VCC= 4.5 V 4.0 ns Minimum hold time, Dn to CP, (th1): TC= +25C, VCC = 4.5 V. 2.5 ns TC= -55C and +125C, VCC= 4.5 V 2.5 ns Minimum hold time, EN to CP, (th2): TC= +25C, VCC = 4.5 V. 2.0 ns TC= -55C and +125C, VCC= 4.5 V 2.0 ns Minimum pulse wi

17、dth CPn high or low (tW1): TC= +25C, VCC = 4.5 V. 6.0 ns TC= -55C and +125C, VCC= 4.5 V 6.0 ns Minimum pulse width clear (CLR) low (tW2): TC= +25C, VCC = 4.5 V. 6.0 ns TC= -55C and +125C, VCC= 4.5 V 7.0 ns Minimum recovery time, CLR to CP (trec): TC= +25C, VCC = 4.5 V. 4.0 ns TC= -55C and +125C, VCC

18、= 4.5 V 4.5 ns Maximum clock frequency, (fmax): TC= +25C, VCC = 4.5 V. 95 MHz TC= -55C and +125C, VCC= 4.5 V 95 MHz 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unle

19、ss otherwise noted, all voltages are referenced to GND. 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 4/ Unless otherwise specified, the values listed above shall apply over the fu

20、ll VCCand TCrecommended operating range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91611 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLIC

21、ABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTME

22、NT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-

23、103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 N

24、on-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 20 - Standard for Description of

25、 54/74ACXXXXX and 54/74ACTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). 2.3 Order of precedence. In the event of a conflict between the text of t

26、his drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device clas

27、ses Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M

28、shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PR

29、F-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logi

30、c diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC

31、UIT DRAWING SIZE A 5962-91611 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and pos

32、tirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.

33、5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. Fo

34、r RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for d

35、evice classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed

36、 manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submi

37、tted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certifica

38、te of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, no

39、tification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review t

40、he manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 38 (see M

41、IL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91611 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical perf

42、ormance characteristics. Test Symbol Test conditions -55C TC +125C +4.5 V VCC +5.5 V Devicetype VCCGroup A subgroups Limits Unit unless otherwise specified Min Max 4.5 V 4.4 VIN= VIHminimum or VILmaximum IOH= -50 A All 5.5 V 5.4 4.5 V 3.7 VIN= VIHminimum or VIL maximum IOH= -24 mA All 5.5 V 4.7 High

43、 level output voltage VOH1/ VIN= VIHminimum or VILmaximum IOH= -50 mA All 5.5 V 1, 2, 3 3.85 V 4.5 V 0.1 V VIN= VIHminimum or VILmaximum IOL= 50 A All 5.5 V 0.1 4.5 V 0.5 VIN= VIHminimum or VILmaximum IOL= 24 mA All 5.5 V 0.5 Low level output Voltage VOL1/ VIN= VIHminimum or VILmaximum IOL= 50 mA Al

44、l 5.5 V 1, 2, 3 1.65 High level input voltage VIH 2/ All 4.5 and 5.5 V 1, 2, 3 2.0 V Low level input voltage VIL 2/ All 4.5 V and 5.5 V 1, 2, 3 0.8 V IILVIN= 0.0 V All 5.5 V -1.0 Input leakage current IIH VIN= 5.5 V All 5.5 V 1, 2, 3 1.0 A Quiescent supply current delta, TTL input levels ICC 3/ For

45、input under test, VIN= VCC- 2.1 V For all other inputs, VIN= VCCor GND All 5.5 V 1, 2, 3 1.6 mA ICCH5.5 V 160 ICCLQuiescent supply current ICCZVIN= VCCor GND IOUT= 0.0 A All 5.5 V 1, 2, 3 160 A Off-state output leakage current, high IOZH OEn = VIHminimum or VILmaximum All other inputs = VCCor GND VO

46、UT= 5.5 V All 5.5 V 1, 2, 3 +10.0 A Off-state output leakage current, low IOZL OEn = VIHminimum or VILmaximum All other inputs = VCCor GND VOUT= 0.0 V All 5.5 V 1, 2, 3 -10.0 A Input capacitance CINSee 4.4.1c TC= +25C All GND 4 4.5 pF Output capacitance COUTSee 4.4.1c TC= +25C All GND 4 4.5 pF Power

47、 dissipation capacitance CPD4/ See 4.4.1c TC= +25C All 5.0 V 4 4.4 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91611 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3

48、990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC +125C +4.5 V VCC +5.5 V Device type VCCGroup A subgroups Limits Unit unless otherwise specified Min Max Functional tests See 4.4.1b All 4.5 V and 5.5 V 7, 8 L H Propagation delay time, CP to On tPHL1CL= 50 pF RL= 500 4.5 V 9 1.0 9.5 ns 5/ See figure 4 All 10, 11 1.0 11.5 tPLH14.5 V 9 1.0 9.5 5/ All 10, 11 1.0 11.5 Propagation delay time, CLR to On tPHL2CL= 50 pF RL= 500 4.5 V 9 1.0 14.5 ns 5/ See figure 4

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1