1、Lessons Learned Entry: 0383Lesson Info:a71 Lesson Number: 0383a71 Lesson Date: 1995-02-15a71 Submitting Organization: JPLa71 Submitted by: J.C. Marr / P.D. LismanSubject: Galileo AACS Computer Memory Access Contention Problem Abstract: Galileo AACS checksum errors resulted from bus contentions cause
2、d by noise from electromagnetic coupling within the AACS intra-subsystem harness. Recommendations included simulations and other methods for thoroughly characterizing the electrical performance of cables.Description of Driving Event: During system level testing, repeated Attitude and Articulation Co
3、ntrol Subsystem (AACS) checksum errors occurred without the presence of actual memory content errors (miscompares). These checksum errors occurred only when in one of the four possible CPU-memory configurations and only when the Command and Data Subsystem (CDS) was accessing the off-line memory. Ext
4、ensive troubleshooting on the spacecraft showed that the anomalous checksum errors were being caused by both AACS memories placing data on the data bus at the same time (bus contention).After further subsystem testing and analysis, subsystem engineers determined that the bus contentions were caused
5、by electromagnetic coupling within the AACS intra-subsystem harness while simultaneously accessing both AACS memories. Specifically, data being placed on the data bus by the on-line memory induced noise on the address lines which caused the off-line memory to turn on its data line drivers during an
6、off-line CDS Direct Memory Access (DMA) cycle.The noise coupling between the Address and Data lines occurred in spite of AACS bay harness design which was in compliance with JPL and Galileo design standards. Further, the limited fidelity CDS simulator used during subsystem testing prevented finding
7、the problem prior to spacecraft integration.Additional Keyword(s): Circuit NoiseProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Reference(s): PFR #44836.Lesson(s) Learned: 1. Design to JPL or project standards is not always sufficient to ensure adequ
8、ate performance of subsystem cabling. In this era of rapid technological change, design standards, used successfully in the past, may not be sufficient to preclude problems in the present.2. Simulators of subsystem interfaces with other subsystems may not always provide adequate performance assessme
9、nt for the spacecraft environment.3. Limited fidelity of simulators used during subsystem testing can prevent diagnosis of subsystem problems prior to spacecraft integration.Recommendation(s): 1. The cognizant engineer must fully consider the electrical performance of the cable in his specific subsy
10、stem application.2. The subsystem impact of simulator limitations should be thoroughly understood and documented. Additionally, testing with integrated breadboards instead of simulators should be encouraged.3. Subsystem equipment must be adequately tested on the spacecraft in all redundant configura
11、tions to ensure that equipment configuration dependent problems are found.4. Noise on intra-subsystem cabling must be thoroughly investigated as to cause and effects as early as possible in subsystem testing.Evidence of Recurrence Control Effectiveness: N/ADocuments Related to Lesson: N/AMission Dir
12、ectorate(s): N/AAdditional Key Phrase(s): a71 Hardwarea71 Test & VerificationProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Additional Info: Approval Info: a71 Approval Date: 1988-09-01a71 Approval Name: Carol Dumaina71 Approval Organization: 125-204a71 Approval Phone Number: 818-354-8242Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
