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4、70 (outside USA) Fax: 724-776-0790 Email: CustomerServicesae.org SAE WEB ADDRESS: http:/www.sae.org SAE values your input. To provide feedback on this Technical Report, please visit http:/www.sae.org/technical/standards/J3076_201510 SURFACE VEHICLE INFORMATION REPORT J3076 OCT2015 Issued 2015-10 Clo
5、ck Extension Peripheral Interface (CXPI) RATIONALE The CXPI protocol is a low speed low cost communication protocol that is capable of reducing wire counts to simple devices like switches and sensors. This document defines an implementation of the CXPI protocol with the focus on enabling ASIC design
6、s commonly found in switches and sensors. FOREWORD The objective of this document is to define a level of information in the implementation of low speed vehicle serial data network communications using the Clock Extension Peripheral Interface (CXPI) protocol. The goal of this document is to provide
7、an overview of the CXPI protocol describing the features and functions of the serial data physical layer, data link layer and application layer for use in the automotive Electronic Control Units (ECU). This standard will allow ECU and tool manufacturers to satisfy the needs of multiple end users wit
8、h minimum modifications to the basic design. This standard will benefit vehicle Original Equipment Manufacturers (OEMs) by achieving lower ECU costs due to higher industry volumes of the basic design. NOTE: Understanding of this document requires the knowledge of the JASO Clock Extension Peripheral
9、Interface (CXPI) specification. SAE INTERNATIONAL J3076 OCT2015 Page 2 of 37 TABLE OF CONTENTS 1. SCOPE 4 1.1 Mission/Theme 4 1.2 Overview . 4 1.3 Relationship to JASO D015 CXPI Specification . 4 2. REFERENCES 4 2.1 Applicable Documents 4 3. DEFINITION OF TERMS 5 3.1 GLOSSARY 5 4. ACRONYMS, ABBREVIA
10、TIONS, AND SYMBOLS 6 4.1 Abbreviations 6 4.2 Symbols 7 5. CXPI PROTOCOL PRINCIPLES 7 5.1 Features 7 5.2 OSI Layer Structure 8 5.3 CXPI Transceiver Functionality . 9 5.3.1 Transceiver Block Diagram and Signal References . 9 5.3.2 Start Bit Falling Edge Timing 10 5.3.3 Internal TXD Signal Delay (relev
11、ant to all nodes) . 10 5.3.4 TX signal Generation 11 5.3.5 Internal Analog Circuitry Delay . 12 5.3.6 Internal FET Switching Delay 14 5.3.7 Internal RXD Signal Generation 15 6. PROTOCOL DESCRIPTION 16 6.1 Application Layer . 16 6.1.1 Overview . 16 6.1.2 Master / Slave Communication . 17 6.1.3 Frame
12、Transfer Management . 17 6.1.4 Frame ID Assignment . 20 6.1.5 Wakeup / Sleep . 20 6.1.6 Multi Clock Master Processing 22 6.2 Data Link Layer . 22 6.2.1 Data Link Layer functional model 22 6.2.2 Frame Types . 24 6.2.3 Universal Asynchronous Receiver Transmitter (UART) Byte Format . 26 6.2.4 Data Tran
13、smission Timing 26 6.2.5 CXPI Bus Access Determination 27 6.2.6 Error Detection 27 6.2.7 Error Handling . 28 6.2.8 CXPI Communication System with CSMA/CR . 28 6.2.9 Clock Signal with Logic 1 State (Idle State) . 32 6.2.10 Clock Signal with Logic 0 State (Start Bit) . 33 SAE INTERNATIONAL J3076 OCT20
14、15 Page 3 of 37 6.3 Physical Layer . 35 6.3.1 Physical Layer functional model . 35 6.3.2 Encoding Unit 35 6.3.3 Decoding Unit 36 6.3.4 Clock Transmission Unit . 36 7. SUMMARY 36 8. NOTES 37 8.1 Revision Indicator 37 Figure 1 CXPI layer structure 8 Figure 2 Block diagram and signal references 9 Figur
15、e 3 Start bit falling edge timing 10 Figure 4 Internal TXD signal delay 11 Figure 5 Internal TX signal generation (master node). 11 Figure 6 Internal TX signal generation (slave node) . 12 Figure 7 Internal analog circuitry delay (master node) 13 Figure 8 Internal analog circuitry delay (slave node)
16、 13 Figure 9 Internal FET switching delay (master node) . 14 Figure 10 InternaL FET switching delay (slave node) . 15 Figure 11 Internal RXD signal generation (master node) . 15 Figure 12 Internal RXD signal generation (slave node) 16 Figure 13 Event trigger method example 18 Figure 14 Polling metho
17、d example 19 Figure 15 Sleep, standby and normal mode management . 21 Figure 16 Data link layer functional model 23 Figure 17 CXPI normal frame structure 25 Figure 18 CXPI sleep frame structure . 25 Figure 19 CXPI long frame structure . 25 Figure 20 UART byte transmission . 26 Figure 21 Inter-frame-
18、space between frame and bus idle state . 26 Figure 22 Inter-byte-space between bytes within a frame 26 Figure 23 Simplified cxpi communication system . 29 Figure 24 Transceiver bit arbitration example . 32 Figure 25 Clock signal with logic 1 state (idle) . 33 Figure 26 Clock signal with logic 0 stat
19、e (start bit) 34 Figure 27 CXPI transceiver block diagram with encoding and decoding unit . 35 Figure 28 Example clock transmission on the communication bus 36 SAE INTERNATIONAL J3076 OCT2015 Page 4 of 37 1. SCOPE 1.1 Mission/Theme This document is an information report and intended to provide an ov
20、erview of the Clock Extension Peripheral Interface (CXPI) protocol. 1.2 Overview This document describes the features and functions of the CXPI protocol. The CXPI protocol provides some selected features of the Controller Area Network (CAN) protocol implemented on a UART-based data link for mainly H
21、MI (Human Machine Interface) of road vehicles electric systems. 1.3 Relationship to JASO D015 CXPI Specification This information report is a description of the CXPI protocol, which is specified in the JASO D015 CXPI document published by JASO. The JASO D015 CXPI specification is the normative refer
22、ence for the CXPI protocol. The CXPI specification is maintained by JSAE (Society of Automotive Engineers of Japan, Inc.). This information report does not supersede any information contained in the JASO D015 CXPI specification. It has the sole purpose of providing textual description and graphical
23、illustrations to ease reading and interpretation of the CXPI protocol. 2. REFERENCES 2.1 Applicable Documents The following publications form a part of this specification to the extent specified herein. Unless otherwise indicated, the latest issue of SAE publications shall apply. 2.1.1 SAE Documents
24、 Available from SAE International, 400 Commonwealth Drive, Warrendale, PA 15096-0001, Tel: 877-606-7323 (inside USA and Canada) or +1 724-776-4970 (outside USA), www.sae.org. SAE J2602/1 LIN Network for Vehicle Applications SAE J2602/2 LIN Network for Vehicle Applications Conformance Test SAE J2602/
25、3 File Structures for a Node Capability File (NCF) 2.1.2 ISO Documents Copies of these documents are available online at http:/webstore.ansi.org/ ISO 11898-1 Road Vehicles + Controller Area Network (CAN) + Part 1: Data Link Layer and Physical Signaling ISO 14230 Road Vehicles + Diagnostic Communicat
26、ion over K-Line (DoK-Line) ISO 17987 Road Vehicles + Local Interconnect Network (LIN) 2.1.3 JASO Documents Copies of these documents are available online at http:/www.jsae.or.jp/index_e.php JASO D015 (all parts), Automobiles H Clock Extension Peripheral Interface (CXPI) SAE INTERNATIONAL J3076 OCT20
27、15 Page 5 of 37 3. DEFINITION OF TERMS 3.1 GLOSSARY 3.1.1 Controller portion which controls processing of a data link layer 3.1.2 Inter Byte Space time between bytes on the communication bus 3.1.3 Inter Frame Space time between frames on the communication bus 3.1.4 Master Node node in the system tha
28、t has the function of schedule management and primary clock master 3.1.5 Clock Master node that transmits the clock to communication bus 3.1.6 Primary Clock Master node that becomes clock master 3.1.7 Secondary Clock Master node that transmits the clock when primary clock master doesnt transmit the
29、clock 3.1.8 Slave Node each node other than master node connected within the CXPI communication system 3.1.9 Schedule information specifying which frame is transmitted at which timing that becomes the origin of periodic transmission 3.1.10 Sequence procedure of transmission and reception of the data
30、 among two or more nodes 3.1.11 Idle State existence of the frame is not recognized on the communication bus. Only the clock exists, and it is possible to transmit frames 3.1.12 PTYPE Field includes the parity bit of “1 bit” and the frame TYPE of 7 bits. 3.1.13 PID Field includes the parity bit of “
31、1 bit” and the frame ID of 7 bits. SAE INTERNATIONAL J3076 OCT2015 Page 6 of 37 3.1.14 Nominal Baud Rate baud rate within the protocol specification range and target value of baud rate actually used 3.1.15 Operational State Supported wakeup/sleep; in the state of normal mode, non-supported wakeup/sl
32、eep; in the state of power-on 4. ACRONYMS, ABBREVIATIONS, AND SYMBOLS 4.1 Abbreviations AP Application Layer CAN Controller Area Network CR Collision Resolution CRC Cyclic Redundancy Check CSMA Carrier Sense Multiple Access CT Counter CXPI Clock eXtension Peripheral Interface DLC Data Length Code DL
33、L Data Link Layer ECU Electronic Control Unit FET Field Effect Transistor HI High HMI Human Machine Interface IBS Inter Byte Space ID Identifier IFS Inter Frame Space Ind Indicator JSAE Society of Automotive Engineers of Japan, Inc. LIN Local Interconnect Network LO Low LSB Least Significant Bit MSB
34、 Most Significant Bit NRZ Non Return to Zero NM Network Management SAE INTERNATIONAL J3076 OCT2015 Page 7 of 37 OP Option OSI Open Systems Interconnection PID Protected ID PL Physical Layer PTYPE Protected TYPE PWM Pulse Width Modulation RX Receive (data) RXD RXD pin of the Transceiver TH Threshold
35、TTL Transistor-Transistor-Logic TX Transmit (data) TXD TXD pin of the Transceiver UART Universal Asynchronous Receiver Transmitter 4.2 Symbols kbit/s Kilobit per second RX(bit) Receive (bit) Tbit Nominal bit time TX(bit) Transmit (bit) 9 s Voltage per microsecond 5. CXPI PROTOCOL PRINCIPLES 5.1 Feat
36、ures The CXPI protocol has been defined with the objective to combine significant features of CAN onto a UART-based data link with a Carrier Sense Multiple Access (CSMA) and Collision Resolution (CR) physical layer transceiver to improve the data exchange communication between ECUs compared to typic
37、al UART-based communication e.g., RS 232, ISO 14230 K-Line, ISO 17987 Local Interconnect Network (LIN). The following is an overview of the CXPI protocol features: x Carrier Sense Multiple Access (CSMA): the CXPI UART transceiver performs bit level arbitration, x Collision Resolution (CR): the CXPI
38、UART transceiver performs bit level collision resolution (avoidance), x Bus master clock synchronization (Pulse Width Modulation (PWM) bit representation) of all nodes on the CXPI communication bus to trigger the slave nodes communication, x Cyclic Redundancy Check (CRC) at the end of each frame, SA
39、E INTERNATIONAL J3076 OCT2015 Page 8 of 37 x Single Master and multiple Slave Node Polling Schedules, x Polling method to support periodic schedules, x Event method to support the responsiveness of slave node communication, x Sleep and Wakeup support, x Maximum baud rate of 20 kbit/s, x Up to 16 nod
40、es connected to a CXPI communication bus, In addition to above feature list very small CXPI devices (nodes) may be equipped without a UART and microcontroller. Those devices can be designed to support the CXPI protocol with a Pulse Width Modulation (PWM)-based communication which is compatible with
41、the CXPI UART-based communication. 5.2 OSI Layer Structure The CXPI protocol is compliant to the JIS X 0026: 1995, Glossary of terms used in information processing (Open Systems Interconnection). Figure 1 shows the CXPI layer structure. The Presentation, Session, Transport and Network Layers are not
42、 part of this Information Report. Figure 1 - CXPI layer structure SAE INTERNATIONAL J3076 OCT2015 Page 9 of 37 5.3 CXPI Transceiver Functionality 5.3.1 Transceiver Block Diagram and Signal References The block diagram of the CXPI Transceiver with the signal references is used as a reference of all t
43、iming diagrams in the following chapters. Each CXPI node implements a CXPI Transceiver which consists of the following function blocks: x (1): TXD signal from Controller: TXD buffer buffers a sending bit sent from the Controller (TTL level signal); x Arbitration Unit: receives the sending bit from t
44、he TXD buffer and performs an arbitration (low bit wins) according to the Carrier Sense Multiple Access (CSMA) and Collision Resolution (CR) method; x (2) TX Encode Unit: TTL signal after arbitration generated as PWM signal which will be transmitted; x (3) TX Analog Unit with bus driver (FET): TX an
45、alog signal as input to the bus driver (FET); x (4) CXPI bus signal: Physical analog waveform of the CXPI bus; x (5) RX Decode Unit: TTL signal generated as output from the comparator as PWM signal; x (6) Decoded RX signal: TTL signal generated from PWM signal as input for Arbitration Unit; x (6) RX
46、D signal to Controller: RXD buffer buffers the received bit (none arbitrated bits) and transmits to the Controller for software comparison with original transmitted byte; Figure 2 shows the block diagram and signal references. No 1 CXPI Node Controller TXD line which transmits bytes from the UART in
47、 TTL level 1 CXPI Node Transceiver TXD line which shows x Tbit delay because of center sampling at (1) 2 Node Encoder logic which performs conversion of NRZ signal from TXD buffer to PWM signal 3 Node Transceiver analog circuit shapes the TTL into an analog signal 4 CXPI communication bus (analog si
48、gnal waveform is interpreted by all connected nodes) 5 Actual CXPI communication bus analog RX signal waveform received by all nodes to be decoded 6 Controller RXD line which receives bytes from the RXD buffer in TTL level 6 Controller RXD line which receives bytes from the Decoder logic Figure 2 -
49、Block diagram and signal references SAE INTERNATIONAL J3076 OCT2015 Page 10 of 37 The block diagram shown in Figure 2 is common for all nodes. But there are two differences between a master and a slave node transceiver which are not illustrated in Figure 2. x The master node transceiver operates based on the clock master (the clock supplied by a controller which is called master internal clock).
