SIS SS IEC 263-1986 Acoustics Scales and sizes for plotting frequency characteristics and polar diagrams《音响效果 频率特性标图及坐标图比例和尺寸》.pdf

上传人:priceawful190 文档编号:1043880 上传时间:2019-03-27 格式:PDF 页数:1 大小:25.07KB
下载 相关 举报
SIS SS IEC 263-1986 Acoustics  Scales and sizes for plotting frequency characteristics and polar diagrams《音响效果 频率特性标图及坐标图比例和尺寸》.pdf_第1页
第1页 / 共1页
亲,该文档总共1页,全部预览完了,如果喜欢就下载吧!
资源描述
展开阅读全文
相关资源
猜你喜欢
  • JEDEC JESD8-4-1993 Center-Tap-Terminated (CTT) Low-Level High- Speed Interface Standard for Digital Integrated Circuits《数字集成电路的CTT低水平高速度接口标准》.pdf JEDEC JESD8-4-1993 Center-Tap-Terminated (CTT) Low-Level High- Speed Interface Standard for Digital Integrated Circuits《数字集成电路的CTT低水平高速度接口标准》.pdf
  • JEDEC JESD8-5A 01-2007 2 5 V (PLUS OR MINUS) 0 2 V (Normal Range) and 1 8 V C 2 7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Ci.pdf JEDEC JESD8-5A 01-2007 2 5 V (PLUS OR MINUS) 0 2 V (Normal Range) and 1 8 V C 2 7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Ci.pdf
  • JEDEC JESD8-6-1995 High Speed Transceiver Logic (HSTL) A 1 5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits《基于数字集成电路接口标准的高速收发器逻辑(HSTL)A 1 5输.pdf JEDEC JESD8-6-1995 High Speed Transceiver Logic (HSTL) A 1 5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits《基于数字集成电路接口标准的高速收发器逻辑(HSTL)A 1 5输.pdf
  • JEDEC JESD8-7A-2006 1 8 V (PLUS OR MINUS) 0 15 V (Normal Range) and 1 2 - 1 95 V (Wide Range) Power Supply Voltage and Interface Standard for Non-Terminated Digital Integrated Circ.pdf JEDEC JESD8-7A-2006 1 8 V (PLUS OR MINUS) 0 15 V (Normal Range) and 1 2 - 1 95 V (Wide Range) Power Supply Voltage and Interface Standard for Non-Terminated Digital Integrated Circ.pdf
  • JEDEC JESD8-8-1996 Stub Series Terminated Logic for 3 3 Volts (SSTL-3)《3 3伏的短系列终止逻辑(SSTL-3)》.pdf JEDEC JESD8-8-1996 Stub Series Terminated Logic for 3 3 Volts (SSTL-3)《3 3伏的短系列终止逻辑(SSTL-3)》.pdf
  • JEDEC JESD8-9B-2002 Stub Series Terminated Logic for 2 5 Volts (SSTL 2)《2 5伏的短系列终止逻辑(SSTL 2) 勘误 2002年10月18日》.pdf JEDEC JESD8-9B-2002 Stub Series Terminated Logic for 2 5 Volts (SSTL 2)《2 5伏的短系列终止逻辑(SSTL 2) 勘误 2002年10月18日》.pdf
  • JEDEC JESD80-1999 Standard for Description of 2 5 V CMOS Logic Devices《2 5 V CMOS逻辑设备的描述标准》.pdf JEDEC JESD80-1999 Standard for Description of 2 5 V CMOS Logic Devices《2 5 V CMOS逻辑设备的描述标准》.pdf
  • JEDEC JESD82-10A-2007 Definition of the SSTU32866 1 8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications《SSTU32866的定义 DDR2 RDIMM应用软件28位1 2注册缓冲器加奇偶校验测试》.pdf JEDEC JESD82-10A-2007 Definition of the SSTU32866 1 8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications《SSTU32866的定义 DDR2 RDIMM应用软件28位1 2注册缓冲器加奇偶校验测试》.pdf
  • JEDEC JESD82-11-2004 Standard for Definition of CU878 PLL Clock Driver for Registered DDR2 DIMM Applications《DDR2 DIMM应用软件中CU878 PLL 时钟驱动器的标准定义》.pdf JEDEC JESD82-11-2004 Standard for Definition of CU878 PLL Clock Driver for Registered DDR2 DIMM Applications《DDR2 DIMM应用软件中CU878 PLL 时钟驱动器的标准定义》.pdf
  • 相关搜索

    当前位置:首页 > 标准规范 > 国际标准 > 其他

    copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
    备案/许可证编号:苏ICP备17064731号-1