1、 Table of Contents Page 1 Scope 2 2 Normative references 2 3 Symbols and abbreviations. 2 4 Introduction . 5 5 Physical specification 6 5.1 Card dimensions, socket configuration and pin numbering. 6 5.2 Write Protect Switch and Card ID 6 5.3 Card Connector . 6 5.4 Labeling . 6 6 Electrical specifica
2、tion. 10 6.1 Overview 10 6.2 Signal Description 10 6.3 Card Type Detection Mechanism 17 6.4 SSM Card bus operation . 17 7 Register Specification . 22 7.1 Overview 22 7.2 Configuration Space Register 22 7.3 SSM Card Specific Register 30 8 Command Specification 38 8.1 Overview 38 8.2 IDENTIFY DEVICE (
3、ECh) 38 8.3 SET FEATURES (EFh) 38 8.4 Bus Master DMA 39 8.5 CARD DATA IN(FEh) 40 9 Performance specification. 44 9.1 Overview 44 9.2 Write Performance. 44 9.3 Read Performance. 44 10 File system specification 45 10.1 File Allocation Table 45 10.2 Directory. 45 10.3 File name . 45 Annex A Bibliograph
4、y. 46 Page 1 of 46 pages RP 2006-2006 SMPTE RECOMMENDED PRACTICE Solid State Media (SSM) Card Specification Copyright 2006 by THE SOCIETY OF MOTION PICTURE AND TELEVISION ENGINEERS 3 Barker Avenue, White Plains, NY 10601 (914) 761-1100 Approved September 15, 2006 RP 2006-2006 Page 2 of 46 pages Fore
5、word SMPTE (the Society of Motion Picture and Television Engineers) is an internationally-recognized standards developing organization. Headquartered and incorporated in the United States of America, SMPTE has members in over 80 countries on six continents. SMPTEs Engineering Documents, including St
6、andards, Recommended Practices and Engineering Guidelines, are prepared by SMPTEs Technology Committees. Participation in these Committees is open to all with a bona fide interest in their work. SMPTE cooperates closely with other standards-developing organizations, including ISO, IEC and ITU. SMPTE
7、 Engineering Documents are drafted in accordance with the rules given in Part XIII of its Administrative Practices. SMPTE Recommended Practice 2006 was prepared by Technology Committee V16. 1 Scope This document defines the specification of the Solid State Media (SSM) Card. The physical specificatio
8、n provides the physical characteristics of the Card and the connector. The electrical interface between a host and the Card is a high performance bus and this document specifies the signal description, the electrical characteristics, and the bus operations. The register specification defines the reg
9、isters for configuration and also defines the specific registers related to interrupt signals or commands. The command specification defines the commands for the bus master data transfer and the sensing log information written in the SSM Card in addition to the ATA commands. To guarantee the perform
10、ance of the SSM Card, requirements for writing and reading speed are specified. The file system for the SSM Card is the FAT system. 2 Normative references The following standards contain provisions, which, through reference in this text, constitute provisions of this standard. At the time of publica
11、tion, the editions indicated were valid. All standards are subject to revision, and parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent edition of the standards indicated below. ANSI INCTIS 361-2002, AT Attachment with Packet Interfa
12、ce -6 (ATA/ATAPI-6) PCI Local Bus Specification Revision 3.0 (Note: The Bylaws of PCI-SIG (section 15) limit the RAND licensing terms to members.) FAT: ISO/IEC 9293, Second Edition, 1994-1 l-l 5, Information Technology Volume and File Structure of Disk Cartridges for Information Interchange 3 Symbol
13、s and abbreviations For symbol definition and abbreviations, the reader is encouraged to study the PCI and ATA specifications. This document uses same terms defined in the mentioned standards and in other referenced documents. ATA AT Attachment ATAPI AT Attachment with Packet Interface FAT File Allo
14、cation Table PCI Peripheral Component Interconnect PCI SIG PCI Special Interest Group RP 2006-2006 Page 3 of 46 pages The following symbols and abbreviations are defined in the Physical specification. N Newton WPS Write Protect Switch The following symbols and abbreviations are defined in the Electr
15、ical specification. LV Low Voltage Vcc Power Vpp Programming and peripheral voltages GND Ground Agent All devices which relates to a data transfer on the bus Master Device which drives the address bus and sends a command Slave Device which receives a command and responses to it Assert Set a signal a
16、ctive Negate Set a signal inactive CCD (SSM) Card Card Detect CVS (SSM) Card Voltage Sense CCLK (SSM) Card Clock which provides timing for all transactions CAD (SSM) Card Address and Data multiplexed bus - During the address phase, CAD contain a byte address. During the data phase CAD contain data.
17、CCBE (SSM) Card Command and Bus Enables multiplexed bus During the address phase CCBE are defined as bus Command. During the data phase, CCBE are used as Byte Enables. CCLKRUN# (SSM) Card Clock Request/Status CDEVSEL# (SSM) Card Device Select CFRAME# (SSM) Card Cycle Frame - While CFRAME# is asserte
18、d, data transfers continue. CGINT (SSM) Card Grant CINT# (SSM) Card Interrupt request CIRDY# (SSM) Card Initiator Ready CPAR# (SSM) Card Even Parity CPERR# (SSM) Card Parity Error CREQ# (SSM) Card Request CRST# (SSM) Card Reset CSERR# (SSM) Card System Error CSTOP# (SSM) Card Stop transaction CTRDY#
19、 (SSM) Card Target ready Transaction Bus cycle which is initiated by an address phase and is followed by data phases. NOTE The acronym “C” stands for (SSM) Card. RP 2006-2006 Page 4 of 46 pages The following symbols and abbreviations are defined in the Register specification. ABRT Abort Indicates th
20、e requested command has been aborted BIST Built-in Self Test BSY Busy Indicates if a device is busy DEV Device select DRDY Device Ready DRQ Data Request Indicates if data transfer is ready between a device and a host EOT End of Table ERR Error Indicates an error occurred during execution of the prev
21、ious command IDNF ID not found INTA# Interrupt A used to request an interrupt IRQ Interrupt request bit which represents an INTRQ signal IRQE Interrupt request enable bit for IRQ INTRQ Interrupt request signal nIEN Enable bit for INTRQ signal LBA Logical Block Addressing Addressing by the linear map
22、ping of sectors PIO Programmed Input/Output RO Read only Res Reserved R/W Read/Write WO Write only scatter/gather Gathering scattered data from memory for transmission SRST Software Reset UNC Uncorrectable The following symbols and abbreviations are defined in the Command specification. CID Card ID
23、CSD Card Specific Data DMA Direct Memory Access RP 2006-2006 Page 5 of 46 pages 4 Introduction Figure 4.1 shows the overall structure of the SSM Card specification and the relationship between the other reference documents and this document. Figure 4.1 Structure of SSM Card specification and relatio
24、n between Reference documents The physical specification defines the Card package dimensions, the Card connector, the write protect switch for protection of files stored on the SSM Card and the Card ID to identify the SSM Card. The electrical interface of the SSM Card is a high performance 32 bit bu
25、s with multiplexed address and data lines. This document specifies the signal descriptions, the electrical characteristics and the bus operations of this SSM Card. The register specification defines the Configuration space registers to identify or control the SSM Card and also defines the specific r
26、egisters related to interruption or commands. The command specifications define the commands required for the SSM Card. Write protection and power management are performed using ATA commands as unique functions for the SSM Card. Data transmission between a SSM Card and a host is performed using the
27、Bus Master DMA transfer commands. After a read or write command is issued from the host, the SSM Card takes initiative of bus control and performs data transfers as the bus master. Furthermore, the commands for sensing log information written in the SSM Card are specified. To guarantee the performan
28、ce of the SSM Card, the writing and reading speeds required for the SSM Card are specified. The SSM Card uses the FAT file system. Physical ATA/ATAPI standard FAT Card/Connector dimension, Write Protect SW, Card IDSSM Card specificationElectrical Interface (Signal description/Characteristics, Operat
29、ion)Command Bus master DMA transfer, Card informationFile systemPCI Local bus specification Register ( Configuration, SSM Card )RP 2006-2006 Page 6 of 46 pages 5 Physical specification 5.1 Card dimensions, socket configuration and pin numbering Figure 5.1 specifies Card package dimensions. Figure 5.
30、2 defines configuration of Card socket contacts and a relative pin contact locations, Figure 5.3 defines the pin connector layout and Figure 5.4 defines the pin connector dimensions. 5.2 Write Protect Switch and Card ID The SSM Card shall be equipped with a Write Protect Switch (WPS) and Card Identi
31、fication (Card ID). The Write Protect Switch shall be located at the approximate position as shown in Figure 5.1. The status of the Write Protect Switch should be sensed by a host with the IDENTIFY DEVICE command (See 8.2) so that the host can perform the write protection functionality depending on
32、the status of the Write Protect Switch. The Card ID shall be located at the approximate position as shown in Figure 5.1. 5.3 Card Connector The socket contacts on the SSM Card shall be located as specified in Figure 5.2. The Card connector socket layout shall match the host pin-connector layout as s
33、hown in Figure 5.3. The Card connector shall contain a top side planer, electrically conductive, ground plate with eight raised dimples 0.5 mm height as shown in Figure 5.4. The mechanical and electrical performance of the Card connector shall be as specified in Table 5.1. Table 5.1 Mechanical and e
34、lectrical performance Item Specification Insertion Force 39.2 N maximum at speed of 25 mm/minute Pulling Force 6.67 N minimum and 39.2 N maximum at speed of 25 mm/minute Contact Resistance Initially 40 m maximum and 20 m maximum change at voltage of 20 mV and current of 1 mA 5.4 Labeling If a label
35、is attached on surface A and/or surface B of a SSM Card, the thickness of the Card including the labels shall not exceed the thickness specified in Figure 5.1. RP 2006-2006 Page 7 of 46 pages INTERCONNECT AREACONNECTOR#34#68Surface ASurface B#1#35MAX 2.50Surface AWPSNote 1 - Polarization key lengthN
36、ote 2 - Dimension R corner radiusNote 3 - Ground clip locationNote 4 - Dimension is increased by 0.50 0.05 mm over dimples1.65 0.0554.00 0.10MIN 10.0MIN 10.01.60 0.051.00 0.052.10 0.0585.60 0.200.60 0.1065.60 0.0579.60 0.05MIN 3.01.00 0.05MAX 5.00Dimensions in millimetersSUBSTRATE AREAReference plan
37、e(Note 1)(Note 2)(Note 3)(Note 4)CARD IDFigure 5.1 SSM Card Package Dimensions RP 2006-2006 Page 8 of 46 pages 0.50 - 2.50PINSOCKET CONTACTMIN 0.940.50 0.1010o- 15oRADIUS INCLUDEDPIN/SOCKET CONTACT AREAMAX 0.46MIN 110o(CONTACT AREA)0.44 0.02 ( PIN DIAMETER )Dimensions in millimetersMAX 0.50Power 5.0
38、0 0.1GeneralDetect4.25 0.13.50 0.1LL2REF 4.50REF 3.75REF 3.00Figure 5.2 SSM Card Socket Configuration Figure 5.3 SSM Card Pin Connector layout RP 2006-2006 Page 9 of 46 pages Figure 5.4 SSM Card Pin Connector Dimensions RP 2006-2006 Page 10 of 46 pages 6 Electrical specification 6.1 Overview This se
39、ction defines the electrical specification of the SSM Card. The electrical interface of the SSM Card is a 32 bit high performance bus (SSM Card bus) with multiplexed address and data lines. The SSM Card bus specifies Card pin assignment and its signal definitions, Card detection mechanism, Electrica
40、l characteristics, Timing parameters and Bus operations. NOTE The bit order of the 32 bit bus shall follow the convention where bit 0 is LSB and bit 31 is MSB. Multi byte values are represented with little endian, the least significant byte first. 6.2 Signal Description 6.2.1 Pin assignment The pin
41、assignment of the SSM Card bus shall be as defined in Table 6.1. Note: The name of the pins is the same as the PCI bus signal name when the first character “C“ is deleted. The differences in the signals are summarized as follows: Card Detect pins and Voltage Sense pins are added. There is no IDSEL (
42、Initialization Device Select) pin. There is only one interrupt pin (CINT#). A clock control signal (CCLKRUN#) is added. RP 2006-2006 Page 11 of 46 pages Table 6.1 SSM Card pin assignment Pin Signal I/O Signal type Pin Signal I/O Signal type 1 GND DC 35 GND DC 2 CAD0 I/O h/z 36 CCD1# Output 3 CAD1 I/
43、O h/z 37 CAD2 I/O h/z 4 CAD3 I/O h/z 38 CAD4 I/O h/z 5 CAD5 I/O h/z 39 CAD6 I/O h/z 6 CAD7 I/O h/z 40 Reserved 7 CCBE0# I/O h/z 41 CAD8 I/O h/z 8 CAD9 I/O h/z 42 CAD10 I/O h/z 9 CAD11 I/O h/z 43 CVS1 I/O 10 CAD12 I/O h/z 44 CAD13 I/O h/z 11 CAD14 I/O h/z 45 CAD15 I/O h/z 12 CCBE1# I/O h/z 46 CAD16 I
44、/O h/z 13 CPAR I/O h/z 47 Reserved 14 CPERR# I/O s/h/z 48 Reserved 15 CGNT# Input 49 CSTOP# I/O s/h/z 16 CINT# Output 0/d 50 CDEVSEL# I/O s/h/z 17 Vcc DC in 51 Vcc DC in 18 Vpp DC in 52 Vpp DC in 19 CCLK Input 53 CTRDY# I/O s/h/z 20 CIRDY# I/O s/h/z 54 CFRAME# I/O s/h/z 21 CCBE2# I/O h/z 55 CAD17 I/
45、O h/z 22 CAD18 I/O h/z 56 CAD19 I/O h/z 23 CAD20 I/O h/z 57 CVS2 I/O 24 CAD21 I/O h/z 58 CRST# Input 25 CAD22 I/O h/z 59 CSERR# Output o/d 26 CAD23 I/O h/z 60 CREQ# Output h/z 27 CAD24 I/O h/z 61 CCBE3# I/O h/z 28 CAD25 I/O h/z 62 Reserved 29 CAD26 I/O h/z 63 Reserved 30 CAD27 I/O h/z 64 CAD28 I/O h
46、/z 31 CAD29 I/O h/z 65 CAD30 I/O h/z 32 Reserved 66 CAD31 I/O h/z 33 CCLKRUN# I/O o/d 67 CCD2# Output 34 GND DC 68 GND DC I/O: Input/Output, h/z: Tri-state, s/h/z :Sustained Tri-State, o/d : Open drain, # : Low active NOTE Sustained Tri-State is an active low tri-state signal owned and driven by one
47、 and only one agent at a time. The detailed information is described in the PCI Local Bus Specification section 2.1. RP 2006-2006 Page 12 of 46 pages 6.2.2 Signal/Pin Description 6.2.2.1 Power and Ground pins Vcc Vcc of the SSM Card shall be 3.3V 0.3V Voltage. Vpp The voltage of the Vpp pin shall be
48、 the same voltage as the Vcc pin. 6.2.2.2 Interface Configuration pins CCD2:1# CCD2:1# are the Card Detect pins that provide a means for sockets to detect the Card insertion and removal events. CCD2:1# pins are at opposite ends of the connector to ensure a valid insertion. CVS2:1# CVS2:1# are in con
49、junction with CCD2:1# and used to encode card type information. NOTE See section 6.3 for details. 6.2.2.3 System pins CCLK CCLK provides timing for all transactions on the SSM Card bus interface and is an input to every SSM Card bus device. All other SSM Card bus signals, except CRST# (upon assertion), CCLKRUN#, CINT#, CCD2:1#, and CVS2:1, are sampled on the rising edge of CCLK, and all timing parame
