1、 TIA-694-1997 APPROVED: JULY 30, 1997 REAFFIRMED: DECEMBER 26, 2001 REAFFIRMED: DECEMBER 7, 2012 TIA-694 August 1997Electrical Characteristics for an Unbalanced Digital Interface for Data Signaling Rates Up to 5 12 kbit/s NOTICE TIA Engineering Standards and Publications are designed to serve the pu
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5、ard or Publication. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and to determine the applicability of regula
6、tory limitations before its use. (From Project No. 3-3692-RF2, formulated under the cognizance of the TIA TR-30.2 Subcommittee on DTE-DCE Interfaces and Protocols.) Published by TELECOMMUNICATIONS INDUSTRY ASSOCIATION Technology (b) there is no assurance that the Document will be approved by any Com
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19、 HEREOF, AND THESE CONTENTS WOULD NOT BE PUBLISHED BY TIA WITHOUT SUCH LIMITATIONS. STDSEIA TIA-bYq-ENGL 1797 323Lib00 0585Clb8 5Dh TINEIA-694 FOREWORD (This foreword is not part of this Standard) This Standard was formulated under the cognizance of TIA Subcommittee TR-30.2 on Data Transmission inte
20、rfaces. This Standard was developed in response to a demand from the data communications community for a simple higher speed unbalanced Interface. Thus, this Standard specifies generators and receivers capable of operating at data signaling rates up to 512 kbitls. Signal quality is also specified. T
21、he generator is similar to the generator specified in TINEIA-423-B and can inter-operate with EIA/TIA-232-E, EIWIA-562 and TINEIA-423-9 receivers. The receiver is similar to the receiver specified in EIA/TIA- 232-E and can inter-operate with EIATIA-232-E, ElMIA-562 and TINEIA-423-6 generators. Noise
22、 margin is reduced from that specified in EIA/TIA-232-E, however, the maximum capacitance load is also reduced, thus limiting cable length more tightly. Noise margin is enhanced over standard logic (TTL) levels, being roughly twice that of TTL. Together the generator I receiver set specified provide
23、s an improved “232“ like interface while supporting high data signaling required by current data circuit- ter min at ing eq u pment . I 1 2 3 4 5 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.3.1 5.3.2 5.3.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 ELECTRICAL CHARACTERISTICS FOR AN . UNBALANCED DIGITAL INTERFACE FOR DAT
24、A SIGNALING RATES UP TO 512 kbit/s CONTENTS Page SCOPE 1 NORM AT1 V E RE FE REN C ES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 DEFINITIONS, SYMBOLS AND ABBREVIATIONS 3 APPLICABILITY ._. 4
25、ELECTRICAL CHARACTERISTICS . . . . 6 Signaling Sense 6 Generator Characteristics . . . . . . . _ . . 7 Open Circuit Output Voltage . . . . . . . . . . . . . _. . 7 Output Voltage Under Load . 7 Short-circuit Output Current . . . . . . . . . . . 8 Output Signai Quality . . 8 Rece ver Character i st i
26、cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input Impedance . . 9 Input Voltage Threshold . ._ . . . . . . . . . . . ._. . . 9 Fail-safe Operation 1 O System Requirements and Consideratio
27、ns ._ . . . . 1 O Interchange Capacitance Limit . . . . . . . . . . . 1 O Interchange Media Propagation Delay 1 O Signal Common . 1 1 Shield Ground 1 1 . 111 Previous page is blank - STD-EIA TIA-by4-ENGL 1997 3234b00 0585070 Lb4 W TINEIA-694 1 SCOPE This Standard specifies the electrical Characteris
28、tics of the unbalanced voltage digital interface circuit, normally implemented in integrated circuit technology, that may be employed when specified for the interchange of serial binary signals between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) or in any point-to-poin
29、t interconnection of serial binary signals between digital equipment. Devices complying to this Standard are electrically compatible with TIAEIA-423-B, ElMIA-562 and ElMIA-232-E interfaces. This Standard is also compatible with !TLi-T Recommendations V.l O and V.28. The interface circuit includes a
30、generator connected by a interconnecting cable to a load consisting of a receiver. The electrical characteristics of the circuit are specified in terms of required voltage, current, and resistance values obtained from direct measurements of the generator and receiver components at the interface poin
31、ts (connector). The logic function of the generator and the receiver is not defined by this Standard, as it is application dependent. Minimum signal quality requirements are also specified to support the specified data signaling rates. It is intended that this Standard will be referenced by other st
32、andards that specify the other necessary components of an interface (e.g, connector, pin assignments, function) for applications where the electrical characteristics of an unbalanced voltage digital interface circuit are required. This Standard does not specify other characteristics of the interface
33、 (such as protocol and timing, etc.) essential for proper operation across the interface. 1 TINEIA-694 2 NORMATIVE REFERENCES The following Standard contains provisions which, through reference in this text, constitute provisions of this Standard. At the time of publication, the edition indicated wa
34、s valid. All standards are subject to revision, and parties to agreements based on this Standard are encouraged to investigate the possibility of applying the most recent edition of the standard indicated below. ANSI and TIA maintain registers of currently valid national standards published by them.
35、 ANSI/EIA/TIA-232-E-I 991, circuit-terminating equipment employing serial binary data interchange. Interface between data terminal equipment and data ANSI/TINEIA-423-B-I 994, interface circuits. Electrical characteristics of unbalanced voltage digital ANSI/EIA/TIA-562-1989, Electrical characteristic
36、s for an unbalanced digital interface. TIAiEIA-404-B-1995, Standard for stat?-stop signal quality for non-synchronous data terminal equipment. ITU-T V. 1 0-1 996, Electrical characteristics for unbalanced double-current interchange circuits for general use with integrated circuit equipment. ITU-T V.
37、28-1988, Electrical characteristics for unbalanced double-current interchange circuits. 2 STD-EIA TIA-bSq-ENGL 1997 323qbUU 0585072 T37 TINEIA-694 3 DEFINITIONS, SYMBOLS AND ABBREVIATIONS For the purposes of this Standard, the following definitions, symbols and abbreviations apply: 3.1 Data signalin
38、g rate Data signaling rate, expressed in the units bit/s (bits per second), is defined as 1/T where T is the minimum interval between two significant instants. 3.2 DTE Data Terminal Equipment 3.3 DCE Data Circuit-Terminating Equipment 3.4 Star (*) Star (*) - represents the opposite input condition f
39、or a parameter. For example, the symbol Q represents the receiver output state for one input condition, while Q* represents the output state for the opposite input state. 3 TINEIA-694 I D I T E I 4 APPLICABILITY D + E = Telecommunications Channel Figure 1 - Applications of unbalanced voltage digital
40、 interface circuit The unbalanced interface circuit will be utilized on data, timing, or control circuits where the data signaling rate is up to 512 kbiVs. Unbalanced voltage digital interface devices meeting the electrical characteristics of this Standard need not operate over the entire data signa
41、ling rate range specified. They may be designed to operate over a narrow range to satisfy more economically specific applications, particularly at the lower data signaling rates. 4 STDmEIA TIA-bSq-ENGL 1797 = 323Lib00 0585074 BOT = TINEIA-694 While the unbalanced interface is intended for use at dat
42、a signaling rates of 512 kbit/s or lower, its general use is not recommended where the following conditions prevail: a. The interconnecting cable length is too long for effective non-terminated unbalanced operation, which occurs when the propagation delay between the generator and receiver is greate
43、r than one half of the generators output voltage transition time (Le., not a transmission line). b. The interconnecting cable is exposed to extraneous noise sources that may cause an unwanted voltage in excess of -tl V measured differentially between the signal conductor and circuit common at the lo
44、ad end of the cable with a 1 O0 R resistor substituted for the generator. c. A configuration other than a simple point-to-point connection between the generator and the single receiver is required (e.g., multi-point, or multi-drop configuration). While a restriction of maximum cable length in not sp
45、ecified, a maximum capacitive load is specified in 5.4.1. This maximum capacitance load does limit the maximum cable length, however, that length is cable construction specific. Additionally, a maximum cable propagation delay is specified in 5.4.2, which also limits the maximum cable length indirect
46、ly. The selected cable length should meet the limits specified in 5.4.1 and 5.4.2 and is not further specified in this Standard. 5 TINEIA-694 5 ELECTRICAL CHARACTERISTICS The unbalanced voltage digital interface circuit is shown in figure 2. The circuit consists of three parts: the generator (G), th
47、e interconnecting cable, and the receiver (R). The electrical characteristics of the generator and receiver are specified in terms of direct electrical measurements while the interconnecting cable is described in terms of its electrical and physical characteristics. GENERATOR INTERCONNECTING LOAD ,i
48、 CABLE RECEIVER - this includes the interface connector and the circuit board capacitance as well as effective device input capacitance. The input capacitance at the interface point shall be measured with a I Vp-p sine wave, with O V bias, and at 500 kHz. The receiver must comply with the input resi
49、stance specified above with up to a maximum voltage of k12 V applied at the receiver interface point. 5.3.2 Input Voltage Thresholds The region between -2.0 V and +2.0 V is defined as the receiver transition region. The signal state is undefined when the voltage is in the transition region. Table 2 lists the threshold voltages as well as the other voltage points for the receiver. The threshold values guarantee a minimum noise margin (MNM) of 1.0 V. This is calculated by subti-actii-ig the threshold voltage from the generator minimum output voltage (3.0 V - 2.0 V
