IEC 60191-6-12-2011 Mechanical standardization of semiconductor devices - Part 6-12 General rules for the preparation of outline drawings of surface mounted semiconductor device pa.pdf

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1、 IEC 60191-6-12 Edition 2.0 2011-06 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardization of semiconductor devices Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guidelines for fine-pitch land grid array (FLGA

2、) Normalisation mcanique des dispositifs semiconducteurs Partie 6-12: Rgles gnrales pour la prparation des dessins dencombrement des botiers des dispositifs semiconducteurs montage en surface Lignes directrices de conception pour les botiers matriciels plots et pas fins (FLGA) IEC 60191-6-12:2011 co

3、lour inside THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2011 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without

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7、e 3, rue de Varemb CH-1211 Geneva 20 Switzerland Email: inmailiec.ch Web: www.iec.ch About the IEC The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes International Standards for all electrical, electronic and related technologies. About

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15、 deux fois par mois les nouvelles publications parues. Disponible en-ligne et aussi par email. Electropedia: www.electropedia.org Le premier dictionnaire en ligne au monde de termes lectroniques et lectriques. Il contient plus de 20 000 termes et dfinitions en anglais et en franais, ainsi que les te

16、rmes quivalents dans les langues additionnelles. Egalement appel Vocabulaire Electrotechnique International en ligne. Service Clients: www.iec.ch/webstore/custserv/custserv_entry-f.htm Si vous dsirez nous donner des commentaires sur cette publication ou si vous avez des questions, visitez le FAQ du

17、Service clients ou contactez-nous: Email: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 60191-6-12 Edition 2.0 2011-06 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardization of semiconductor devices Part 6-12: General rules for the preparation of outline drawings of surfa

18、ce mounted semiconductor device packages Design guidelines for fine-pitch land grid array (FLGA) Normalisation mcanique des dispositifs semiconducteurs Partie 6-12: Rgles gnrales pour la prparation des dessins dencombrement des botiers des dispositifs semiconducteurs montage en surface Lignes direct

19、rices de conception pour les botiers matriciels plots et pas fins (FLGA) INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE R ICS 31.080.01 PRICE CODE CODE PRIX ISBN 978-2-88912-527-2 Registered trademark of the International Electrotechnical Commission Marque dpose

20、 de la Commission Electrotechnique Internationale colour inside 2 60191-6-12 IEC:2011 CONTENTS FOREWORD . 3 1 Scope . 5 2 Normative references . 5 3 Terms and definitions . 5 4 Terminal position numbering . 6 5 Nominal package dimension . 6 6 Outline drawings and principle dimensions . 7 7 Dimension

21、s 10 Figure 1 Flange-type FLGA 6 Figure 2 Rectangle-type FLGA . 6 Figure 3 Flange-type FLGA 7 Figure 4 Rectangle-type FLGA . 8 Figure 5 Mechanical gauge drawing e . 9 Figure 6 Pattern of terminal position area f. 9 Table 1 Group 1: Dimensions appropriate to mounting and interchangeability 10 Table 2

22、 Group 2: Dimensions and tolerances . 14 Table 3 Combination list of D, E, M D , and M E e = 0,80mm pitch . 15 Table 4 Combination list of D, E, M D , and M E e = 0,65 mm pitch . 16 Table 5 Combination list of D, E, M D , and M E e = 0,50 mm pitch . 17 Table 6 Combination list of D, E, M D , and M E

23、 e = 0,40 mm pitch . 18 Table 7 Combination list of D, E, M D , and M E e = 0,30 mm pitch . 19 60191-6-12 IEC:2011 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-12: General rules for the preparation of outline drawings of surface mounted sem

24、iconductor device packages Design guidelines for fine-pitch land grid array (FLGA) FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to pr

25、omote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guide

26、s (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non- governmental organizations liaising with the IEC a

27、lso participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as pos

28、sible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. W

29、hile all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertak

30、e to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC itself does not provide any attesta

31、tion of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any services carried out by independent certification bodies. 6) All users should ensure that they have the latest edition of

32、this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or

33、indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable fo

34、r the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 60191-6-12 has be

35、en prepared by subcommittee 47D: Mechanical standardization of semiconductor devices, of IEC technical committee 47: Semiconductor devices. This second edition of IEC 60191-6-12 cancels and replaces the first edition, published in 2002 and constitutes a technical revision. This edition includes the

36、following significant changes with respect to the previous edition: a) scope is expanded so that this standard include the square type FLGA. The title of this standard has been changed accordingly: “Rectangular type” has been deleted from the title. b) ball pitch of 0,3 mm has been added; c) datum i

37、s changed from the body datum to the ball datum; d) combination lists of D, E, M D , and M Ehave been revised. 4 60191-6-12 IEC:2011 The text of this standard is based on the following documents: CDV Report on voting 47D/784/CDV 47D/795/RVC Full information on the voting for the approval of this sta

38、ndard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all the parts in the IEC 60191 series, under the general title Mechanical standardization of semiconductor devices, can be found on

39、the IEC website. The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication. At this date, the publication will be reconfirmed, withdrawn, r

40、eplaced by a revised edition, or amended. IMPORTANT The colour inside logo on the cover page of this publication indicates that it contains colours which are considered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer. 6019

41、1-6-12 IEC:2011 5 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guidelines for fine-pitch land grid array (FLGA) 1 Scope This part of IEC 60191 provides standard outline dra

42、wings, dimensions, and recommended variations for all fine-pitch land grid array packages (FLGA) with terminal pitch of 0,8 mm or less. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited appli

43、es. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60191(all parts), Mechanical standardization of semiconductor devices IEC 60191-6, Mechanical standardization of semiconductor devices Part 6: General rules for the preparation of outlin

44、e drawings of surface mounted semiconductor device packages 3 Terms and definitions For the purposes of this document, the terms and definitions given IEC 60191 series and the following apply. 3.1 fine-pitch land grid array FLGA package with metal lands on one side of a substrate in a matrix of at l

45、east three rows and three columns on a pitch of 0,8 mm or less, wherein the maximum standoff height is 0,10 mm or less NOTE Terminals may be missing from some row-column intersections. 3.2 flange-type FLGA FLGA with a package outline (length, width) defined by a package flange part, mostly substrate

46、, extending outward beyond the perimeter of a molded part or of a flip-chip-bonded part NOTE Flange-type FLGA, shown in Figure 1, is generally cut by singulation press, thus resulting in larger dimensional errors than the singulation by dicing saw 6 60191-6-12 IEC:2011 Figure 1 Flange-type FLGA 3.3

47、rectangle-type FLGA FLGA with a package outline (length, width) defined by a molded part with no extending flange part NOTE Rectangle-type FLGA, shown in Figure 2, is generally cut by dicing, thus resulting in less dimensional errors than the singulation by press machine. Figure 2 Rectangle-type FLG

48、A 4 Terminal position numbering When a package is viewed from the terminal side with the index corner in the bottom left corner position, terminal rows are lettered from bottom to top starting with A, then B, C, AA, AB, etc, whereas terminal columns are numbered from left to right starting with 1. T

49、erminal positions are designated by a row-column grid system and shown as alphanumeric identification, e.g., A1, B1. The letters I, O, Q, S, X and Z shall not be used for naming the terminal rows. 5 Nominal package dimension A nominal package dimension is defined as “the package width (E) length (D)”, which is expressed in the tenths place in mi

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