1、 IEC 60749-29 Edition 2.0 2011-04 INTERNATIONAL STANDARD NORME INTERNATIONALE Semiconductor devices Mechanical and climatic test methods Part 29: Latch-up test Dispositifs semiconducteurs Mthodes dessai mcaniques et climatiques Partie 29: Essai de verrouillage IEC 60749-29:2011 THIS PUBLICATION IS C
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16、: Email: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 60749-29 Edition 2.0 2011-04 INTERNATIONAL STANDARD NORME INTERNATIONALE Semiconductor devices Mechanical and climatic test methods Part 29: Latch-up test Dispositifs semiconducteurs Mthodes dessai mcaniques et climatiques Partie 29:
17、 Essai de verrouillage INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE T ICS 31.080.01 PRICE CODE CODE PRIX ISBN 978-2-88912-434-3 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale
18、2 60749-29 IEC:2011 CONTENTS FOREWORD . 3 1 Scope and object 5 2 Terms and definitions . 5 3 Classification and levels . 8 3.1 Classification . 8 3.2 Levels . 8 4 Apparatus and material 8 4.1 Latch-up tester 8 4.1.1 General . 8 4.1.2 V supplyand their qualification method. 9 4.1.3 Trigger source qua
19、lification method . 9 4.2 Automated test equipment (ATE) . 10 4.3 Heat source . 10 5 Procedure 10 5.1 General latch-up test procedure 10 5.2 Detailed latch-up test procedure 13 5.2.1 I-test 13 5.2.2 V supplyovervoltage test 17 5.2.3 Testing dynamic devices . 19 5.2.4 DUT disposition . 19 5.2.5 Recor
20、d keeping . 19 6 Failure criteria 20 7 Summary 20 Annex A (informative) Examples of special pins that are connected to passive components 21 Annex B (informative) Calculation of operating ambient or operating case temperature for a given operating junction temperature 23 Figure 1 V supplyqualificati
21、on circuit 9 Figure 2 Trigger source qualification circuit 10 Figure 3 Latch-up test flow . 11 Figure 4 Test waveform for positive I-test 14 Figure 5 Test waveform for negative I-test . 15 Figure 6 Equivalent circuit for positive input/output I-test latch-up testing 16 Figure 7 Equivalent circuit fo
22、r negative input/output I-test latch-up testing . 17 Figure 8 Test waveform for V supplyovervoltage 18 Figure 9 Equivalent circuit for V supplyovervoltage test latch-up testing . 19 Figure A.1 Examples of special pins that are connected to passive components 22 Table 1 Test matrix a. 12 Table 2 Timi
23、ng specifications for I-test and V supplyovervoltage test . 13 60749-29 IEC:2011 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ SEMICONDUCTOR DEVICES MECHANICAL AND CLIMATIC TEST METHODS Part 29: Latch-up test FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization
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33、tention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights.
34、 IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 60749-29 has been prepared by IEC technical committee 47: Semiconductor devices. This second edition cancels and replaces the first edition published in 2003 and constitutes a technical revis
35、ion. The significant changes with respect to the previous edition include: a number of minor technical changes; the addition of two new annexes covering the testing of special pins and temperature calculations. 4 60749-29 IEC:2011 The text of this standard is based on the following documents: FDIS R
36、eport on voting 47/2083/FDIS 47/2090/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all parts in the IEC 60749 serie
37、s, under the general title Semiconductor devices Mechanical and climatic test methods, can be found on the IEC website. The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC web site under “http:/webstore.iec.ch“ in the da
38、ta related to the specific publication. At this date, the publication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. 60749-29 IEC:2011 5 SEMICONDUCTOR DEVICES MECHANICAL AND CLIMATIC TEST METHODS Part 29: Latch-up test 1 Scope and object This part of IEC 60749 covers the
39、I-test and the overvoltage latch-up testing of integrated circuits. This test is classified as destructive. The purpose of this test is to establish a method for determining integrated circuit (IC) latch- up characteristics and to define latch-up failure criteria. Latch-up characteristics are used i
40、n determining product reliability and minimizing “no trouble found“ (NTF) and “electrical overstress“ (EOS) failures due to latch-up. This test method is primarily applicable to CMOS devices. Applicability to other technologies must be established. The classification of latch-up as a function of tem
41、perature is defined in 3.1 and the failure level criteria are defined in 3.2 2 Terms and definitions For the purposes of this document, the following terms and definitions apply. 2.1 cool-down time period of time between successive applications of trigger pulses or the period of time between the rem
42、oval of the V supplyvoltage and the application of the next trigger pulse (See Figures 4, 5, and 8 and Table 2.) 2.2 device under test DUT semiconductor product subjected to latch-up test 2.3 ground GND common or zero-potential pin(s) of the DUT NOTE 1 Ground pins are not latch-up tested. NOTE 2 A g
43、round pin is sometimes called V ss . 2.4 input pins all address, data-in control, V refand similar pins 2.5 I/O (bi-directional) pins device pins that can be made to operate as an input or output or in a high-impedance state 6 60749-29 IEC:2011 2.6 I supplytotal supply current in each V supplypin (o
44、r pin group) with the DUT biased as indicated in Table 1 2.7 I-test latch-up test that supplies positive and negative current pulses to the pin under test 2.8 latch-up state in which a low-impedance path resulting from an overstress that triggers a parasitic thyristor structure, persists after remov
45、al or cessation of the triggering condition NOTE 1 The overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or any other abnormal condition that causes the parasitic thyristor structure to become regenerative. NOTE 2 Latch-up will not damage the device pro
46、vided that the current through the low-impedance path is sufficiently limited in magnitude or duration. 2.9 logic-high level within the more positive (less negative) of the two ranges of logic levels chosen to represent the logic states NOTE 1 For digital devices, a voltage level equal to V supplyis
47、 used for latch-up testing, except where otherwise specified in the relevant specification. NOTE 2 For non-digital devices, V supply voltage level or the maximum operating voltage that can be applied to that pin as defined in the relevant specification may be used for latch-up testing. 2.10 logic-lo
48、w level within the more negative (less positive) of the two ranges of logic levels chosen to represent the logic states NOTE 1 For digital devices, ground voltage level is used for latch-up testing, except where specified in the relevant specification. NOTE 2 For non-digital devices, ground voltage
49、level or the minimum operating voltage that can be applied to that pin as defined in the relevant specification may be used for latch-up testing. 2.11 maximum V supplymaximum operating voltage for operation within performance specifications NOTE 1 The maximum voltage is not the absolute maximum voltage beyond which permanent damage is likely. NOTE 2 Maximum refers to the magnitude of V supplya
