1、 IEC 62433-2 Edition 2.0 2017-01 INTERNATIONAL STANDARD NORME INTERNATIONALE EMC IC modelling Part 2: Models of integrated circuits for EMI behavioural simulation Conducted emissions modelling (ICEM-CE) Modles de circuits intgrs pour la CEM Partie 2: Modles de circuits intgrs pour la simulation du c
2、omportement lors de perturbations lectromagntiques Modlisation des missions conduites (ICEM-CE) IEC 62433-2:2017-01(en-fr) colour inside THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2017 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publication may be
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20、MC IC modelling Part 2: Models of integrated circuits for EMI behavioural simulation Conducted emissions modelling (ICEM-CE) Modles de circuits intgrs pour la CEM Partie 2: Modles de circuits intgrs pour la simulation du comportement lors de perturbations lectromagntiques Modlisation des missions co
21、nduites (ICEM-CE) INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE 31.200; 33.100.10 ISBN 978-2-8322-3876-9 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale Warning! Make sure that
22、you obtained this publication from an authorized distributor. Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agr. colour inside 2 IEC 62433-2:2017 IEC 2017 CONTENTS FOREWORD . 7 1 Scope 9 2 Normative references 9 3 Terms, definitions, abbreviations and co
23、nventions . 9 3.1 Terms and definitions 9 3.2 Abbreviations 11 3.3 Conventions 11 4 Philosophy . 11 4.1 General . 11 4.2 Conducted emission from core activity (digital culprit) . 12 4.3 Conducted emission from I/O activity 12 4.4 Data exchange format . 12 5 ICEM-CE basic components 13 5.1 General .
24、13 5.2 Internal Activity (IA) 13 5.2.1 General . 13 5.2.2 Examples of IA 14 5.3 Passive Distribution Network (PDN) 14 5.3.1 General . 14 5.3.2 Examples of PDN 15 6 IC macro-models . 16 6.1 Types of IC macro-models 16 6.2 General IC macro-model . 16 6.3 Block-based IC macro-model 17 6.3.1 Block compo
25、nent . 17 6.3.2 Inter-Block Coupling component (IBC) . 18 6.3.3 Block-based IC macro-model structure 19 6.4 Sub-model-based IC macro-model 21 6.4.1 Sub-model component . 21 6.4.2 Sub-model-based IC macro-model structure 22 7 CEML format . 23 7.1 General . 23 7.2 CEML structure . 24 7.3 Global keywor
26、ds . 24 7.4 Header section 24 7.5 Lead definitions 25 7.6 SPICE macro-models 26 7.7 Validity section . 28 7.7.1 General . 28 7.7.2 Attribute definitions 29 7.8 PDN 31 7.8.1 General . 31 7.8.2 Attribute definitions 32 7.8.3 Description 36 7.9 IBC . 40 7.9.1 General . 40 IEC 62433-2:2017 IEC 2017 3 7.
27、9.2 Attribute definitions 40 7.10 IA 42 7.10.1 General . 42 7.10.2 Attribute definitions 42 7.10.3 Description 46 8 Requirements for parameter extraction 47 8.1 General . 47 8.2 Environmental extraction constraints . 47 8.3 IA parameter extraction . 47 8.4 PDN parameter extraction . 47 8.5 IBC param
28、eter extraction 48 Annex A (normative) Preliminary definitions for XML representation 49 A.1 XML basics . 49 A.1.1 XML declaration . 49 A.1.2 Basic elements 49 A.1.3 Root element . 49 A.1.4 Comments . 50 A.1.5 Line terminations . 50 A.1.6 Element hierarchy 50 A.1.7 Element attributes . 50 A.2 Keywor
29、d requirements 50 A.2.1 General . 50 A.2.2 Keyword characters . 51 A.2.3 Keyword syntax . 51 A.2.4 File structure . 51 A.2.5 Values . 53 Annex B (normative) CEML valid keywords and usage . 56 B.1 Root element keywords . 56 B.2 File header keywords 57 B.3 Validity section keywords 58 B.4 Global keywo
30、rds . 59 B.5 Lead Keyword . 59 B.6 Lead_definitions section attributes 60 B.7 Macromodels section attributes . 60 B.8 Pdn section keywords . 61 B.8.1 Lead element keywords . 61 B.8.2 Netlist section keywords 63 B.9 Ibc section keywords . 63 B.9.1 Lead element keywords . 63 B.9.2 Netlist section keyw
31、ords 65 B.10 Ia section keywords 65 B.10.1 Lead element keywords . 65 B.10.2 Voltage section keywords 66 B.10.3 Current section keywords 68 Annex C (informative) Example of ICEM-CE macro-model in CEML format 70 C.1 General . 70 C.2 PDN and IBC sub-model . 70 C.3 IA sub-model 71 4 IEC 62433-2:2017 IE
32、C 2017 C.4 Frequency domain ICEM-CE in CEML . 73 C.5 Time domain ICEM-CE in CEML . 75 Annex D (informative) Conversions between parameter types 77 D.1 General . 77 D.2 Conversion for one-port PDN 77 D.3 Conversion for two-port PDN 77 Annex E (informative) Model parameter generation 79 E.1 General .
33、79 E.2 Default structure and values . 79 E.2.1 General . 79 E.2.2 IA parameters 79 E.2.3 PDN parameters 80 E.3 Model parameter generation from design information 81 E.3.1 General . 81 E.3.2 IA parameters 81 E.3.3 PDN parameters 85 E.4 Model parameter generation from measurements 87 E.4.1 IA paramete
34、rs 87 E.4.2 PDN parameters 90 Annex F (informative) Decoupling capacitors optimization 100 Annex G (informative) Conducted emission prediction . 102 Annex H (informative) Conducted emission prediction at PCB level . 103 Bibliography 105 Figure 1 Decomposition example of a digital IC for conducted em
35、issions analysis . 12 Figure 2 IA component in the case of a current source . 13 Figure 3 Example of IA characteristics in the time domain 14 Figure 4 Example of IA characteristics in the frequency domain . 14 Figure 5 Example of a four-terminal PDN using lumped elements 15 Figure 6 Example of a sev
36、en-terminal PDN using distributed elements 16 Figure 7 Example of a twelve-terminal PDN using matrix representation 16 Figure 8 General IC macro-model 17 Figure 9 Example of block component with a single IA . 18 Figure 10 Example of block components for I/Os . 18 Figure 11 Example of IBC with four i
37、nternal terminals 19 Figure 12 Relationship between blocks and IBC . 19 Figure 13 Block-based IC macro-model 20 Figure 14 Example of block-based IC macro-model 21 Figure 15 Example of simple sub-model . 21 Figure 16 Sub-model-based IC macro-model . 22 Figure 17 CEML inheritance hierarchy . 23 Figure
38、 18 Example of a netlist file defining a sub-circuit . 28 Figure 19 PDN represented as S-parameters in Touchstone format 38 Figure 20 Simulated IA waveform with corresponding parameters 45 Figure A.1 Multiple XML (CEML) files . 52 IEC 62433-2:2017 IEC 2017 5 Figure A.2 XML files with data files (*.d
39、at) . 52 Figure A.3 XML files with additional files 53 Figure C.1 Example pin-out of a microcontroller and the modelled pins 70 Figure C.2 PDN sub-model topology 71 Figure C.3 IA sub-model topology 72 Figure C.4 IA of digital block in frequency domain 72 Figure C.5 IA of digital block in time domain
40、 73 Figure E.1 Typical characterization current gate schematic 82 Figure E.2 Current peak during switching transition . 82 Figure E.3 Example of IA extraction procedure from design . 83 Figure E.4 Technology Influence 83 Figure E.5 Final current waveform for a program period . 84 Figure E.6 Comparis
41、on between measurement and simulation . 84 Figure E.7 Example lumped element model of a package. 85 Figure E.8 Circuit structure of the netlist 87 Figure E.9 Principle of the IA computation in the frequency domain . 88 Figure E.10 Process involved to model i A (t) . 89 Figure E.11 i Ext (t) measured
42、 using IEC 61967-4 . 89 Figure E.12 i A (t)and i Ext (t) profiles 90 Figure E.13 Conventional one-port S-parameter measurement . 90 Figure E.14 Two-port method for low impedance measurement 91 Figure E.15 Two-port method for high impedance measurement 91 Figure E.16 Example of a hardware set-up used
43、 to extract the PDN parameters 92 Figure E.17 Miniature 50 coaxial connectors 93 Figure E.18 Impedance probe using two miniature coaxial connectors . 93 Figure E.19 Open and short terminations . 93 Figure E.20 Measurement probe model 94 Figure E.21 De-embedding principle 94 Figure E.22 Example of a
44、predefined PDN structure 95 Figure E.23 RL configuration 96 Figure E.24 RLC configuration . 97 Figure E.25 RLC with magnetic coupling configuration . 97 Figure E.26 Impedance seen from Vcc and Gnd. 97 Figure E.27 Complete PDN component 98 Figure E.28 Set-up for correlation (left), measurement and pr
45、ediction model (right) . 99 Figure E.29 Set-up used to measure the internal decoupling capacitor 99 Figure F.1 Equivalent schematic of the complete electronic system . 100 Figure F.2 Impedance prediction and measurements . 101 Figure G.1 IEC 61967-4 test set-up standard . 102 Figure G.2 Comparison b
46、etween prediction and measurement . 102 Figure H.1 Prediction of ETVddc noise level at PCB level 103 Figure H.2 Good agreements on the noise envelope 104 6 IEC 62433-2:2017 IEC 2017 Table 1 Attributes of Lead keyword in the Lead_definitions section 25 Table 2 Compatibility between the Mode and Type
47、fields for correct CEML annotation . 26 Table 3 Subckt definition 26 Table 4 Definition of the Validity section 28 Table 5 Definition of the Lead keyword for Pdn section 32 Table 6 Valid data formats and their default units in the Pdn section 35 Table 7 Valid file extensions in the Pdn section . 35
48、Table 8 Valid fields of the Lead keyword in the Pdn section . 36 Table 9 Netlist definition 39 Table 10 Differences between the Pdn and Ibc section fields . 41 Table 11 Valid fields of the Lead keyword for IBC definition . 41 Table 12 Definition of the Lead keyword in the Ia section . 42 Table 13 Voltage and Current definition . 43 Table 14 Valid file extensions in the Ia section . 43 Table 15 Definition of the Pulse keyword in the Voltage or Current section 44 Table 16 Base units of the Pulse sections fields 44 Table 17 Valid data formats and their default units for the Vol
