1、 INTERNATIONAL STANDARD IEC62050First edition2005-07IEEE 1076.6VHDL Register Transfer Level (RTL) synthesis Reference number IEC 62050(E):2005 IEEE Std. 1076.6(E):2004 Publication numbering As from 1 January 1997 all IEC publications are issued with a designation in the 60000 series. For example, IE
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7、 Customer Service Centre If you have any questions regarding this publication or need further assistance, please contact the Customer Service Centre: Email: custserviec.ch Tel: +41 22 919 02 11 Fax: +41 22 919 03 00 VHDL Register Transfer Level (RTL) synthesis INTERNATIONAL STANDARD IEC62050First ed
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15、: IEEE Std FDIS Report on voting 1076.6 (2004) 93/212/FDIS 93/217/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives. The committee has dec
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34、 possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any patent rights in connection therewith. The IEEE shall not be responsible for identifyin
35、g patents for which a license may be required by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention. IEC 62050:2005(E)IEEE 1076.6-2004(E) 4 Published by IEC under licence from IEEE. 2005 IEEE. All rights reserved. IEEE Sta
36、ndard for VHDL Register Transfer Level (RTL) SynthesisSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyApproved 25 August 2004American National Standard InstituteApproved 12 May 2004IEEE-SA Standards BoardAbstract: This document specifies a standard for use of very high-speed i
37、ntegrated circuit hard-ware description language (VHDL) to model synthesizable register-transfer level digital logic. Astandard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset ofthe VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL
38、constructsare identified that should be ignored or flagged as errors.Keywords: hardware description language, logic synthesis, register transfer level (RTL), very high-speed integrated circuit hardware description language (VHDL)IEC 62050:2005(E)IEEE 1076.6-2004(E) 5 Published by IEC under licence f
39、rom IEEE. 2005 IEEE. All rights reserved. This standard describes a standard syntax and semantics for VHDL RTL synthesis. It defines the subset ofIEC/IEEE 61691-1-1:2004 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subsetfor the synthesis domain. This standard is based
40、 on IEC/IEEE 61691-1-1:2004, IEEE Std 1164TM-1993, and IEEE Std 1076.3TM-1997.The purpose of this standard is to define a syntax and semantics that can be used in common by all compliantRTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools useIEC/IEEE 616
41、91-1-1:2004 This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of a particular synthesis implementation by making their designscompliant with this standard.The standard is intended for use by logic designers and electronic engine
42、ers.This document specifies IEEE Std 1076.6-2004, which is a revision of IEEE Std 1076.6-1999. The VHDLSynthesis Interoperability Working Group (SIWG) of the IEEE Computer Society started the developmentof IEEE Std 1076.6-2004 in January 1998. The work initially started as a Level 2 effort (Level 1
43、beingIEEE Std 1076.6-1999). In fact the work on Level 2 continued right after Level 1 was completed by theworking group. The working group realized that a Level 2 was required and that it would take some time todevelop and continued working on it at regular face-to-face meetings and teleconferences.
44、 As the Level 2draft continued to mature, the working group decided that rather than having two different levels of synthe-sis subsets, it was better to just have one standard, with IEEE Std 1076.6-2004 becoming Level 2.The intent of this version was to include a maximum subset of VHDL that could be
45、 used to describe synthe-sizable RTL logic. This included considering new features introduced by IEC/IEEE 61691-1-1:2004, new semantics based on algorithmic styles rather than template-driven, and a set of synthesis attributes that could be used to annotate an RTL description. The following team lea
46、ders drove this effort:Syntax: Lance ThompsonSemantics: Vinaya SinghAttributes: Sanjiv NarayanIn addition, the following provided much-needed additional support:Web and reflector admin: David BishopDocumentation: John Michael WilliamsA majority of the work conducted by the working group was done via
47、 teleconferencing, which was held reg-ularly and open to all. Also, the working group used an e-mail reflector and its web page effectively todistribute and share information.IEEE IntroductionIEC 62050:2005(E)IEEE 1076.6-2004(E) 6 Published by IEC under licence from IEEE. 2005 IEEE. All rights reser
48、ved. The following volunteers contributed to the development of this standard:J. Bhasker, ChairJim Lewis, Vice-ChairDevelopment of IEEE Std 1076.6-1999Initial work on this standard started as a synthesis interoperability working group under VHDL Interna-tional. The working group was also chartered b
49、y the EDA Industry Council Project Technical AdvisoryBoard (PTAB) to develop a draft based on the donated subsets by the following companies/groups: Cadence European Synthesis Working GroupIBM Mentor Graphics SynopsysAfter the PTAB approved of the draft 1.5 with an overwhelming affirmative response, an IEEE PAR wasobtained to clear its way for IEEE standardization. Most of the members of the original group continued tobe part of the Pilot Group under P1076.6 to lead the technical work.At the time the 1999 standard wa
