1、 IEEE Standard for Universal Verification Methodology Language Reference Manual Sponsored by the Design Automation Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA IEEE Computer Society IEEE Std 1800.2-2017 IEEE Std 1800.2-2017IEEE Standard for Universal Verification Methodology La
2、nguage Reference ManualSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyApproved 14 February 2017IEEE-SA Standards BoardThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2017 by The Institute of Electrical and Electr
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31、vised thatdetermination of the validity of any patent rights, and the risk of infringement of such rights, is entirely theirown responsibility. Further information may be obtained from the IEEE Standards Association.6Copyright 2017 IEEE. All rights reserved.ParticipantsThe Universal Verfication Meth
32、olodogy (UVM) Working Group is entity based. At the time this standardwas completed, the Universal Verfication Metholodogy (UVM) Working Group had the followingmembership:Tom Alsop, ChairHillel Miller, Vice ChairChristeen Gray, SecretaryJoe Daniels, Technical EditorThe following members of the entit
33、y balloting committee voted on this standard. Balloters may have votedfor approval, disapproval, or abstention. When the IEEE-SA Standards Board approved this standard on 14 February 2017, it had the followingmembership:Jean-Philippe Faure, ChairVacant position, Vice ChairJohn D. Kulick, Past ChairK
34、onstantinos Karachalios, Secretary*Member EmeritusJamsheed AgahiMala BandyopahdyayMartin BarnasconiDennis BrophyJoel FeldmanTom FitzpatrickCourtney FricanoMark GlasserChristeen GrayShuang HanShobhit KapoorAdiel KhanJustin ReficeUwe SimmMark StricklandSrivatsa VasudevanKarl WhitingAccellera Systems I
35、nitiative, Inc.Advanced Micro Devices (AMD)Analog Devices Inc.Cadence Design Systems, Inc.Cisco Systems, Inc.IBMIntel CorporationMentor GraphicsNVIDIA CorporationNXP SemiconductorsSemifore, Inc.Southwest Jiaotong UniversitySynopsys, Inc.Verific Design Automation, Inc.Chuck AdamsMasayuki AriyoshiTed
36、BurseStephen DukesDoug EdwardsJ. Travis GriffithGary HoffmanMichael JanezicThomas KoshyJoseph L. Koepfinger*Kevin LuDaleep MohlaDamir NovoselRonald C. PetersenAnnette D. ReillyRobby RobsonDorothy StanleyAdrian StephensMehmet UlemaPhil WennblomHoward WolfmanYu Yuan7Copyright 2017 IEEE. All rights res
37、erved.IntroductionVerification has evolved into a complex project that often spans internal and external teams, but thediscontinuity associated with multiple, incompatible methodologies among those teams can limitproductivity. The Universal Verification Methodology (UVM) Language Reference Manual (L
38、RM)addresses verification complexity and interoperability within companies and throughout the electronicsindustry for both novice and advanced teams while also providing consistency. While UVM is revolutionary,being the first verification methodology to be standardized, it is also evolutionary, as i
39、t is built on the OpenVerification Methodology (OVM), which combined the Advanced Verification Methodology (AVM) withthe Universal Reuse Methodology (URM) and concepts from the e Reuse Methodology (eRM).Furthermore, UVM also infuses concepts and code from the Verification Methodology Manual (VMM),pl
40、us the collective experience and knowledge of the over 300 members of the Accellera UVM WorkingGroup to help standardize verification methodology. Finally, the transaction level modeling (TLM) facilitiesin UVM are based on what was developed by Open SystemC Initiative (OSCI) for SystemC, though they
41、 arenot an exact replication or re-implementation of the SystemC TLM library.This introduction is not part of IEEE Std 1800.2-2017, IEEE Standard for Universal Verification MethodologyLanguage Reference Manual.8Copyright 2017 IEEE. All rights reserved.9Copyright 2017 IEEE. All rights reserved.Conten
42、ts1. Overview 131.1 Scope 131.2 Purpose. 131.3 Conventions used. 132. Normative references. 163. Definitions, acronyms, and abbreviations 163.1 Definitions . 163.2 Acronyms and abbreviations . 174. UVM class reference . 185. Base classes 205.1 Overview 205.2 uvm_void . 205.3 uvm_object. 205.4 uvm_tr
43、ansaction. 315.5 uvm_port_base #(IF) 365.6 uvm_time . 406. Reporting classes . 436.1 Overview 436.2 uvm_report_message . 436.3 uvm_report_object . 466.4 uvm_report_handler. 526.5 Report server 556.6 uvm_report_catcher . 597. Recording classes. 657.1 uvm_tr_database 657.2 uvm_tr_stream . 677.3 UVM li
44、nks . 718. Factory classes . 768.1 Overview 768.2 Factory component and object wrappers . 768.3 UVM factory 8210Copyright 2017 IEEE. All rights reserved.9. Phasing. 899.1 Overview 899.2 Implementation 899.3 Phasing definition classes 899.4 uvm_domain 989.5 uvm_bottomup_phase 999.6 uvm_task_phase. 10
45、09.7 uvm_topdown_phase . 1019.8 Predefined phases 10210. Synchronization classes . 10710.1 Event classes 10710.2 uvm_event_callback 11010.3 uvm_barrier 11110.4 Pool classes 11310.5 Objection mechanism 11410.6 uvm_heartbeat 11910.7 Callbacks classes 12111. Container classes 12611.1 Overview 12611.2 u
46、vm_pool #(KEY,T) 12611.3 uvm_queue #(T). 12812. UVM TLM interfaces 13112.1 Overview 13112.2 UVM TLM 1 13112.3 UVM TLM 2 14813. Predefined component classes . 16813.1 uvm_component. 16813.2 uvm_test. 18113.3 uvm_env. 18213.4 uvm_agent 18213.5 uvm_monitor 18313.6 uvm_scoreboard. 18313.7 uvm_driver #(R
47、EQ,RSP) . 18413.8 uvm_push_driver #(REQ,RSP) . 18413.9 uvm_subscriber 18511Copyright 2017 IEEE. All rights reserved.14. Sequences classes 18714.1 uvm_sequence_item. 18714.2 uvm_sequence_base. 19114.3 uvm_sequence #(REQ,RSP) 20014.4 uvm_sequence_library . 20115. Sequencer classes. 20615.1 Overview 20
48、615.2 Sequencer interface 20615.3 uvm_sequencer_base . 21115.4 Common sequencer API 21715.5 uvm_sequencer #(REQ,RSP). 21815.6 uvm_push_sequencer #(REQ,RSP) . 21916. Policy classes . 22016.1 uvm_policy 22016.2 uvm_printer 22216.3 uvm_comparer . 23716.4 uvm_recorder . 24316.5 uvm_packer 25116.6 uvm_co
49、pier 25717. Register layer . 26017.1 Overview 26017.2 Global declarations 26018. Register model . 26418.1 uvm_reg_block 26418.2 uvm_reg_map 27618.3 uvm_reg_file 28418.4 uvm_reg . 28618.5 uvm_reg_field 30318.6 uvm_mem 31418.7 uvm_reg_indirect_data 32818.8 uvm_reg_fifo . 32918.9 uvm_vreg . 33218.10 uvm_vreg_field 34218.11 uvm_reg_cbs 34718.12 uvm_mem_mam 35212Copyright 2017 IEEE. All rights reserved.19. Register layer interaction with RTL design. 36119.1 Generic register operation descriptors . 36119.2 Classes for adapting between register and bus operations. 36519.3 u
