1、 IEEE Standard Format for LSI-Package-Board Interoperable Design Sponsored by the Design Automation Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA IEEE Computer Society IEEE Std 2401-2015 IEEE Std 2401-2015 IEEE Standard Format for LSI-Package-Board Interoperable Design Sponsor D
2、esign Automation Standards Committee of the IEEE Computer Society Approved 3 September 2015 IEEE-SA Standards Board Copyrights and Permissions The following figures are reprinted with permission from JEITA1 Figure i, Figure ii, Figure 1, Figure 3, Figure 16, Figure 17, Figure 18, Figure 19, Figure 2
3、0, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, Figure 38, Figure 39, Figure 40, Figure 41, Figure 42, Figure 43, Figure 44, Figure 45, Figure 46, Figure 47,
4、Figure 48, Figure 49, Figure 50, Figure 51, Figure 60, Figure 61, Figure 62, Figure 63, Figure B.1, Figure B.3, Figure B.5, Figure B.6, Figure B.7, Figure B.8, Figure B.10, Figure B.11, Figure B.12, Figure B.13, Figure B.14, Figure B.15, Figure B.16, Figure B.17, Figure B.18, Figure B.19, Figure B.2
5、0, Figure B.21, Figure B.22, Figure B.23, Figure B.24, Figure B.25, Figure B.26, Figure B.27, Figure B.28, Figure B.29 Abstract: A method is provided for specifying a common interoperable format for electronic systems design. The format provides a common way to specify information/data about the pro
6、ject management, netlists, components, design rules, and geometries used in Large-Scale Integrated Circuit-Package-Board designs. The method provides the ability to make electronic systems a key consideration early in the design process; design tools can use it to exchange information/data seamlessl
7、y. Keywords: common interoperable format, components, design analysis, design rules, geometries, IEEE 2401, large-scale integrated circuits, netlists, packages for LSI circuits, printed circuit board, project management, Verilog-HDL 1Every effort has been made to secure permission to reprint borrowe
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38、embership: Yoshinori Fukuba, Chair Yukio Masuko, Vice Chair Takahiro Aoki Bradley Brim Norman Chang John Ellis Tadaaki Hitomi Hiroshi Ishikawa Takashi Otsuki John Park Herb Reiter Genichi Tanaka Atsushi Tomishima The following members of the entity balloting committee voted on this standard. Ballote
39、rs may have voted for approval, disapproval, or abstention. Cadence Design Systems, Inc. Japan Electronics and Information Technology Industries Association (JEITA) Marvell Semiconductor, Inc. Synopsys, Inc. Toshiba Corporation When the IEEE-SA Standards Board approved this standard on 3 September 2
40、015, it had the following membership: John D. Kulick, Chair Jon Walter Rosdahl, Vice Chair Richard H. Hulett, Past Chair Konstantinos Karachalios, Secretary Masayuki Ariyoshi Ted Burse Stephen Dukes Jean-Philippe Faure J. Travis Griffith Gary Hoffman Michael Janezic Joseph L. Keopfinger David J. Law
41、 Hung Ling Andrew Myles T. W. Olsen Glenn Parsons Ronald C. Petersen Annette D. Reilly Stephen J. Shellhammer Adrian P. Stephens Yatin Trivedi Philip Winston Don Wright Yu Yuan Daidi Zhong *Member Emeritus Copyright 2015 IEEE. All rights reserved. vi Introduction This introduction is not part of IEE
42、E Std 2401-2015, IEEE Standard Format for LSI-Package-Board Interoperable Design. To deal with the increasing difficulty of design and the cost competitiveness of the global market, and to shorten the development term, innovative design methodologies should be implemented. It has been difficult to a
43、chieve the optimization of an entire set of large-scale integrated (LSI) circuits, packages, and board (LPB) using individual design processes for each LPB part. One possibility for optimization is to have a certain section design the whole LPB; however, gathering knowledge and integrating the desig
44、n environment of each LPB part is difficult. Dedicated professional technicians of individual LPB parts, who have the best knowledge and performance of their own parts design tools, intend to create design optimization by having proper interoperable information exchanges among all LPB parties. In or
45、der to achieve a design that optimizes the balance between cost and performance, information about and the results of design should be well shared among cooperating LPB design sections. The Japan Electronics and Information Technology Industries Association (JEITA) LPB Interoperable Design Process W
46、orking Group (LPB-WG) was established to identify the solution. The LPB-WG intends to make a standard for an exchange format to make it easy to exchange information between each of the LPB design departments, so that optimal design will be carried out quickly. The LPB interoperable design process ha
47、s the following issues: Netlist not unified on each LPB Complexity of the representation of the relationship as a whole arrangement of the LPB Differences in how to give the design constraints, lack of design information, and many discrepancies in design rules. Databases not unified in each LPB, or
48、among different vendors No unified terms Various problems caused by these issues include the following: A large effort is required for conversion of formats. The occurrence of conversion errors and connection errors is difficult to detect because there is a lack of the information needed to do so. I
49、t takes a long time to gather information, resulting in a long period of design and analysis. It is difficult to make optimal design changes because the entire verification process is difficult. EDA tool cost increase because of additional development required to support multiple formats. It is time-consuming for designers to communicate their intentions in a way that others understand. Based on this analysis, the LPB-WG has established an interface format that can address these issues. As the one of the case studies of the LPB interoperable design process,
