1、g44g40g40g40g3g54g87g71g3g38g25g21g17g22g24g140g16g21g19g20g19g11g53g72g89g76g86g76g82g81g3g82g73g44g40g40g40g3g54g87g71g3g38g25g21g17g22g24g16g20g28g27g26g12g44g40g40g40g3g54g87g68g81g71g68g85g71g3g55g72g86g87g3Mg72g87hg82dg86g73g82g85g3g36g89g68g79g68g81g70g75g72g3g45g88g81g70g87g76g82g81g3g54g72g
2、80g76g70g82g81g71g88g70g87g82g85g54g88g85g74g72-g51g85g82g87g72g70g87g76g89g72g3g39g72g89g76g70g72g3g38g82g80g83g82g81g72g81g87g86g44g40g40g40g3g51g82g90g72g85g3g9g3g40g81g72g85g74g92g3g54g82g70g76g72g87g92g3g54g83g82g81g86g82g85g72g71g3g69g92g3g87g75g72g54g88g85g74g72g3g51g85g82g87g72g70g87g76g89g7
3、2g3g39g72g89g76g70g72g86g3g38g82g80g80g76g87g87g72g72g44g40g40g40g22g3g51g68g85g78g3g36g89g72g81g88g72g3g49g72g90g3g60g82g85g78g15g3g49g60g3g20g19g19g20g25g16g24g28g28g26g15g3g56g54g36g3g3g22g20g3g36g88g74g88g86g87g3g21g19g20g19g38g25g21g17g22g24g55g48IEEE Std C62.35- 2010(Revision ofIEEE Std C62.35
4、-1987)IEEE Standard Test Methodsfor Avalanche Junction Semiconductor Surge-Protective Device ComponentsSponsorSurge Protective Devices Committeeof theIEEE Power for example, failure in the short-circuit fault mode. However, system objectives of other users can require that a particular device should
5、 failin an open-circuit fault mode in order to achieve the desired performance of the system.Thus, failure in the short-circuit fault mode, while considered “fail-safe” by many users, may in fact beconsidered just the opposite by other users. Therefore, the recommended practice is to describe the fa
6、ilure byone of the modes defined above.The device may be equipped with a mechanism that becomes short circuited at an extreme or abnormallyhigh temperature condition. 8. Derived parameters and other test procedures.8.1 Breakdown voltage (V(BR) test (See Figure 5)The purpose of this test is to determ
7、ine the breakdown voltage of an ABD at a specified current level. Apulse of specified width and breakdown current, IT, amplitude shall be applied and the stabilized value ofbreakdown voltage, V(BR), measured near the pulse. The heating effect of this test should not change themeasured voltage by mor
8、e than the accuracy of the voltage measurement. In the absence of specialrequirements, it is recommended a 1 mA test current, IT, with a pulse width of less than 400 ms be used forbreakdown voltages higher than 8 V. Lower breakdown voltage devices may use a higher test current, IT, of10 mA and a cor
9、respondingly reduced current pulse width.This electrical characteristic is specified as a voltage range for the specified test conditions.PS Power supply (accurate pulsed current source for IT)A Track and hold ammeter DVMDigital voltmeter or oscilloscopeABDPS DVMAV(BR)ITIEEE Std C62.35-2010IEEE Stan
10、dard Test Methods for Avalanche Junction SemiconductorSurge-Protective Device Components11Copyright 2010 IEEE. All rights reserved.Figure 5Test circuit for verifying breakdown voltage (V(BR)8.2 Rated peak impulse power (PPPM)This parameter is the product of the peak pulse current multiplied by the c
11、lamping voltage. Determination ofthis parameter requires the simultaneous measurement of both peak pulse current and maximum clampingvoltage, which may not be coincident in time with the impulse current for any given waveform.8.3 Rated average power dissipation (PM(AV)This parameter is specified by
12、the manufacturer in order to limit device temperatures for reliable long life,taking into consideration two parameters:a) Average input current through the junction by repetitive transients, usually indicated by a dutycycle.b) The thermal resistance of the device to the environment by leads or heat-
13、sink mounting or both asrecommended by the manufacturer. Thermal resistance is usually expressed as K/W with C/W asan alternative.8.4 Capacitance (C, CJ) The capacitance shall be measured at a specified signal level, frequency, and bias voltage. NOTEIn the absence of a specific requirement, a signal
14、 level of 10 mV RMS, a frequency of 1 MHz and a DC bias ofzero are recommended for this test.8.5 Insertion loss This test is conducted to determine the loss of transmitted power at a specified frequency, or frequencyrange, caused by the insertion of an ABD into a circuit. It is important for any sys
15、tem carrying acommunication signal.8.5.1 General considerationsThe insertion loss measured for an ABD is strongly dependent on the impedances of the source and the load,and on frequency. Insertion loss specified for an ABD shall therefore include a description of the source andload impedances, as a
16、function of frequency. The range of frequencies over which the measurements aremade shall be suitable for the application.In selecting the impedances for the measurement, consider that the insertion loss in a specific applicationcould be significantly different from that specified for the device, if
17、 either the impedance of the source, orthe load, or both is different from those used in developing the device specification. Therefore theimpedances used in characterizing the insertion loss of the ABD should reflect the application. Incommunications circuits, the source and load impedances are gen
18、erally taken to be the characteristicimpedance of the cabling.The ABD shall be tested at the specified ambient temperature.A bias voltage or current can affect the capacitance of an ABD. If present in the application, a bias voltageshall be applied to the ABD.IEEE Std C62.35-2010IEEE Standard Test M
19、ethods for Avalanche Junction Semiconductor Surge-Protective Device Components12Copyright 2010 IEEE. All rights reserved.Figure 6Circuit for measuring insertion loss (see Clause 2)8.5.2 MeasurementNetwork analyzers can make measurements of insertion loss directly, without need for the calculation. I
20、fsuch equipment is not available the following procedure can be used.a) Set up the circuit as shown in Figure 6. Here the source is shown as having a voltage VSand animpedance ZS. The load impedance is shown as ZL. The source and the load impedance shall equalthe characteristic impedance of the syst
21、em.b) With the position X-Y as shown in Figure 6 open, measure VXY1at each specified frequency. Theninsert the ABD at position XY as shown in Figure 6, and measure the voltage VXY2at eachspecified frequency.c) Calculate the power for each measurement as follows:PXY1= (VXY1) / ZLPXY2= (VXY2) / ZLd) T
22、he insertion loss in decibels at each specified frequency is given by the formula:Insertion Loss = 10 log (PXY1/ PXY2)At frequencies over 1 MHz uncontrolled stray reactances in the test setup can reduce the accuracy of theinsertion loss measurement. IEEE Std C62.36-2000, describes Insertion Loss mea
23、surement methods (Figure 4, configuration 2B).8.6 Voltage overshoot (VOS) (See Figure 7)Overshoot voltage (VOS) is the peak voltage (V1) minus the clamping voltage (VC) of the ABD. This highervoltage is referred to as “overshoot”. This overshoot is primarily attributable to the inductance, LS, of th
24、eABD packaging.Thus, measurements of clamping voltage at steep front and high peak currents shall include steps to reduceerrors due to measurement circuit lead length and loop coupling.ZSVSZLXYSource TestPositionVoltageMeasuringInstrumentVXYIEEE Std C62.35-2010IEEE Standard Test Methods for Avalanch
25、e Junction SemiconductorSurge-Protective Device Components13Copyright 2010 IEEE. All rights reserved.8.7 Overshoot duration, TOS(see Figure 7)Overshoot duration is the time period (t3 tC) from when the clamping voltage, VC, is first exceeded towhen the overshoot voltage decreases to or below the cla
26、mping voltage level. Response time and overshootduration may be a function of the waveform used for the measurement. Except for special applications, aseparate test for response time and overshoot duration is not a necessary design test.Figure 7Voltage overshoot and overshoot duration8.8 Rated forwa
27、rd surge current (IFSM)The purpose of this test is to verify that the device under test is not significantly degraded when subjected toIFSM. Historically this test has used a half sine wave (8.3 ms or 10 ms) current surge applied in the forwarddirection of the unidirectional ABD suppressor.8.8.1 Rat
28、ed forward surge current test method (See Figure 8)a) Apply a half cycle of the rated forward surge current (IFSM) through the unidirectional ABD in theforward direction.b) Repeat the test described in step a), above, for a total of 10 times with a maximum interval betweensurges of 2 minutes. c) Mea
29、sure the stand-by current (ID) as describe in 6.7. The stand-by current (ID) shall not be greaterthan the maximum specified value after the surges.VCDevice clamping voltage for specified current and wave shapeVOSVoltage overshoot (V1VC)TOSOvershoot duration timet1Time for device voltage to reach its
30、 peak overshoot valuet1 t0Response timet3 tCOvershoot durationV1VCVOSVCTOStCt0t1t3TimeABDVoltageIEEE Std C62.35-2010IEEE Standard Test Methods for Avalanche Junction Semiconductor Surge-Protective Device Components14Copyright 2010 IEEE. All rights reserved.Figure 8Test circuit for forward surge curr
31、ent8.9 Forward voltage (VF) (See Figure 8)The forward voltage is measured by applying a specified current (IF) in the forward direction of theunidirectional ABD suppressor. The wave shape of IFcan be an 8.3 ms or 10 ms half sine wave, 300 ssquare pulse or impulse.Figure 9Example of steady state powe
32、r and peak pulse power derating curves for ABDPG Pulse generator RVResistor, value set to give IFSMA Peak reading ammeterDVM Peak reading digital voltmeterABDPG DVMAVFSMIFSMRV0 25 50 75 100 125 150 175 2000255075100Temperature CRating%PeakAverageIEEE Std C62.35-2010IEEE Standard Test Methods for Ava
33、lanche Junction SemiconductorSurge-Protective Device Components15Copyright 2010 IEEE. All rights reserved.8.10 Temperature derating (See Figure 9)Temperature derating describes the variations in either peak (non-repetitive) or steady-state (average) ABDratings with increasing temperatures above a sp
34、ecified base temperature. Steady-state ratings derate from100 % to zero at the maximum junction temperature, TJM. Peak ratings may operate the ABD junction aboveTJMfor limited durations. As a result, peak ratings can derate at a slower rate than steady state ratings.However, the elevated base temper
35、ature for peak ratings cannot exceed TJMand the derated value must bezero at TJM.8.10.1 Temperature derating test method (See Figure 3) The purpose of this test is to verify a derated IPPMor PPPMvalue at an elevated base temperate.a) Place the device under test in the middle of the oven with all nec
36、essary wiring connections securedfor the surge test. Set the oven temperature to the desired elevated base temperature and allow thedevice to reach thermal equilibrium. Thermal equilibrium may be verified by taking consecutivemeasurements of a temperature sensitive characteristic, such as V(BR)as de
37、fined in 8.1, at 5 minintervals. When consecutive values differ by less than the equipment measurement accuracy, ther-mal equilibrium has been reached.b) To verify the derated IPPMvalue, apply 10 pulses of the derated IPPMwaveform with an intervalbetween each pulse application of 30 s maximum. After
38、 testing and cooling to room ambient, theABD shall not have any degradation or catastrophic fault modes. c) To verify the derated PPPMvalue, the test must apply sufficient IPPto make the product of themeasured VCand applied IPPequal to the derated PPPMvalue. For linear IPPMderating to TJM, themaximu
39、m possible IPPvalue, IPPX, would be IPPMmultiplied by temperature difference of TJMandthe desired base temperature divided by temperature difference of TJMand the specified basetemperature. To allow a safety margin, the first applied impulse should be 0.5 IPPXfor measuringthe value of VC. Based on t
40、he calculated IPPVCvalue, the applied value of IPPshall be progressivelyincreased on subsequent impulses until the derated value of PPPMis reached. A further nine pulsesof the derated value of PPPMare then applied to the ABD with a 30 s interval between each. Aftertesting and cooling to room ambient
41、, the ABD shall not have any degradation or catastrophic faultmodes.8.11 Temperature coefficient of breakdown voltage When measuring the temperature with the thermocouple mounted at the specified reference point. The ABDmust be protected against the cooling effects of the circulating heating medium.
42、8.11.1 The test Method of temperature coefficient of breakdown voltage, V(BR)(see Figure 5)This test shall be performed in an oven having adequate temperature stability and a faster thermal responsethan the tested ABD to insure compliance with the intent of this test procedure.a) Place the device un
43、der test in the middle of the oven with all necessary wiring connections. Set theoven temperature at 25 C and allow the device to reach thermal equilibrium. Thermal equilibriummay be verified by taking consecutive measurements of a temperature sensitive characteristic, suchas V(BR)as defined in 8.1,
44、 at 5 min intervals. When consecutive values differ by less than the equip-ment measurement accuracy, thermal equilibrium has been reached. b) Measure and record V(BR) value for 25 C.c) Increase the oven temperature to 45 C and allow the device under test to reach thermal equilibrium.Measure and rec
45、ord breakdown voltage, V(BR2), value for 45 C. The breakdown voltage, V(BR2)will be larger than the 25 C value due to higher initial junction temperature.IEEE Std C62.35-2010IEEE Standard Test Methods for Avalanche Junction Semiconductor Surge-Protective Device Components16Copyright 2010 IEEE. All r
46、ights reserved.d) Repeat item c) for progressively increasing temperatures, recording the corresponding values ofbreakdown voltage. The series of measurements is stopped when the maximum required test temper-ature is reached. Similarly the testing is repeated for decreasing temperatures below 25 C.e
47、) Curve fit the V(BR)versus temperature data. For two temperatures, within the measured range, witha temperature difference of T causing a V(BR)change of V(BR), the temperature coefficient ofbreakdown voltage is:V(BR)=1000 x V(BR)/ T mV/Cor 100 x V(BR)/(V(BR)x T)%/CNOTEAlternatives to mV/C and %/C a
48、re mV/K and %/K.Unless otherwise noted at temperature settings are 5 C.IEEE Std C62.35-2010IEEE Standard Test Methods for Avalanche Junction SemiconductorSurge-Protective Device Components17Copyright 2010 IEEE. All rights reserved.Annex A(informative) BibliographyB1 IEC 60060-1 (1989-11) Ed. 2.0, Hi
49、gh-Voltage Test TechniquesPart 1: General Definitions and TestRequirements.3B2 IEC 60068-1 (1988- 06) Ed. 6.0, Environmental Testing Part 1: General and Guidance.B3 IEC 60068-2-6 (1995-03) Ed. 6.0, Environmental TestingPart 2-6: TestsTest FC: Vibration(Sinusoidal).B4 IEC 60068-2-14 (1984-01) Ed. 5.0, Environmental TestingPart 2-14: TestsTest N: Change ofTemperature.B5 IEC 60068-2-18 (2000-10) Ed. 2.0, Environmental TestingPart 2-18: TestsTest R and Guidance:Water.B6 IEC 60068-2-20 (1979-01) Ed. 4.0, Environmental Test
