1、Semiconductor devices - Mechanical and climatic test methodsPart 26: Electrostatic discharge (ESD) sensitivity testing - Human body model (HBM)(IEC 60749-26:2018)BS EN IEC 60749-26:2018BSI Standards PublicationWB11885_BSI_StandardCovs_2013_AW.indd 1 15/05/2013 15:06EUROPEAN STANDARD NORME EUROPENNE
2、EUROPISCHE NORM EN IEC 60749-26 March 2018 ICS 31.080.01 Supersedes EN 60749-26:2014 English Version Semiconductor devices - Mechanical and climatic test methods -Part 26: Electrostatic discharge (ESD) sensitivity testing -Human body model (HBM) (IEC 60749-26:2018) Dispositifs semiconducteurs - Mtho
3、des dessais mcaniques et climatiques - Partie 26: Essai de sensibilit aux dcharges lectrostatiques (DES) - Modle du corps humain (HBM) (IEC 60749-26:2018) Halbleiterbauelemente - Mechanische und klimatische Prfverfahren - Teil 26: Prfung der Empfindlichkeit gegen elektrostatische Entladungen (ESD) -
4、 Human Body Model (HBM) (IEC 60749-26:2018) This European Standard was approved by CENELEC on 2018-02-19. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alter
5、ation. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language
6、made by translation under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czec
7、h Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the Un
8、ited Kingdom. European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels 2018 CENELEC All rights of exploitation in any form and by any m
9、eans reserved worldwide for CENELEC Members. Ref. No. EN IEC 60749-26:2018 E National forewordThis British Standard is the UK implementation of EN IEC 60749-26:2018. It is identical to IEC 60749-26:2018. It supersedes BS EN 60749-26:2014, which is withdrawn.The UK participation in its preparation wa
10、s entrusted to Technical Committee EPL/47, Semiconductors.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. The
11、British Standards Institution 2018 Published by BSI Standards Limited 2018ISBN 978 0 580 97604 9ICS 31.080.01Compliance with a British Standard cannot confer immunity from legal obligations. This British Standard was published under the authority of the Standards Policy and Strategy Committee on 30
12、April 2018.Amendments/corrigenda issued since publicationDate Text affectedBRITISH STANDARDBS EN IEC 60749-26:2018EUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN IEC 60749-26 March 2018 ICS 31.080.01 Supersedes EN 60749-26:2014 English Version Semiconductor devices - Mechanical and climatic tes
13、t methods -Part 26: Electrostatic discharge (ESD) sensitivity testing -Human body model (HBM) (IEC 60749-26:2018) Dispositifs semiconducteurs - Mthodes dessais mcaniques et climatiques - Partie 26: Essai de sensibilit aux dcharges lectrostatiques (DES) - Modle du corps humain (HBM) (IEC 60749-26:201
14、8) Halbleiterbauelemente - Mechanische und klimatische Prfverfahren - Teil 26: Prfung der Empfindlichkeit gegen elektrostatische Entladungen (ESD) - Human Body Model (HBM) (IEC 60749-26:2018) This European Standard was approved by CENELEC on 2018-02-19. CENELEC members are bound to comply with the C
15、EN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management C
16、entre or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same st
17、atus as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuan
18、ia, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom. European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotech
19、nische Normung CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels 2018 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members. Ref. No. EN IEC 60749-26:2018 E BS EN IEC 60749-26:2018EN IEC 60749-26:2018 (E) 2 European foreword The tex
20、t of document 47/2438/FDIS, future edition 4 of IEC 60749-26, prepared by IEC/TC 47 “Semiconductor devices“ was submitted to the IEC-CENELEC parallel vote and approved by CENELEC as EN IEC 60749-26:2018. The following dates are fixed: latest date by which the document has to be implemented at nation
21、al level by publication of an identical national standard or by endorsement (dop) 2018-11-19 latest date by which the national standards conflicting with the document have to be withdrawn (dow) 2021-02-19 This document supersedes EN 60749-26:2014. Attention is drawn to the possibility that some of t
22、he elements of this document may be the subject of patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights. Endorsement notice The text of the International Standard IEC 60749-26:2018 was approved by CENELEC as a European Standard without any modification.
23、In the official version, for Bibliography, the following notes have to be added for the standards indicated: IEC 60749 (series) NOTE Harmonized as EN 60749 (series). IEC 60749-27 NOTE Harmonized as EN 60749-27. BS EN IEC 60749-26:2018EN IEC 60749-26:2018 (E) 2 European foreword The text of document
24、47/2438/FDIS, future edition 4 of IEC 60749-26, prepared by IEC/TC 47 “Semiconductor devices“ was submitted to the IEC-CENELEC parallel vote and approved by CENELEC as EN IEC 60749-26:2018. The following dates are fixed: latest date by which the document has to be implemented at national level by pu
25、blication of an identical national standard or by endorsement (dop) 2018-11-19 latest date by which the national standards conflicting with the document have to be withdrawn (dow) 2021-02-19 This document supersedes EN 60749-26:2014. Attention is drawn to the possibility that some of the elements of
26、 this document may be the subject of patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights. Endorsement notice The text of the International Standard IEC 60749-26:2018 was approved by CENELEC as a European Standard without any modification. In the officia
27、l version, for Bibliography, the following notes have to be added for the standards indicated: IEC 60749 (series) NOTE Harmonized as EN 60749 (series). IEC 60749-27 NOTE Harmonized as EN 60749-27. 2 IEC 60749-26:2018 IEC 2018 CONTENTS FOREWORD . 5 1 Scope 7 2 Normative references 7 3 Terms and defin
28、itions 7 4 Apparatus and required equipment 10 4.1 Waveform verification equipment 10 4.2 Oscilloscope . 11 4.3 Additional requirements for digital oscilloscopes . 11 4.4 Current transducer (inductive current probe) . 11 4.5 Evaluation loads . 11 4.6 Human body model simulator 12 4.7 HBM test equipm
29、ent parasitic properties . 12 5 Stress test equipment qualification and routine verification 12 5.1 Overview of required HBM tester evaluations 12 5.2 Measurement procedures 13 5.2.1 Reference pin pair determination . 13 5.2.2 Waveform capture with current probe 13 5.2.3 Determination of waveform pa
30、rameters 14 5.2.4 High voltage discharge path test 17 5.3 HBM tester qualification 17 5.3.1 HBM ESD tester qualification requirements . 17 5.3.2 HBM tester qualification procedure 17 5.4 Test fixture board qualification for socketed testers 18 5.5 Routine waveform check requirements 19 5.5.1 Standar
31、d routine waveform check description 19 5.5.2 Waveform check frequency 19 5.5.3 Alternate routine waveform capture procedure . 20 5.6 High voltage discharge path check 20 5.6.1 Relay testers . 20 5.6.2 Non-relay testers . 20 5.7 Tester waveform records. 20 5.7.1 Tester and test fixture board qualifi
32、cation records 20 5.7.2 Periodic waveform check records 20 5.8 Safety . 21 5.8.1 Initial set-up . 21 5.8.2 Training . 21 5.8.3 Personnel safety 21 6 Classification procedure 21 6.1 Devices for classification 21 6.2 Parametric and functional testing 21 6.3 Device stressing . 21 6.4 Pin categorization
33、 . 22 6.4.1 General . 22 6.4.2 No connect pins . 22 6.4.3 Supply pins 23 6.4.4 Non-supply pins . 23 BS EN IEC 60749-26:2018IEC 60749-26:2018 IEC 2018 3 6.5 Pin groupings 24 6.5.1 Supply pin groups 24 6.5.2 Shorted non-supply pin groups 24 6.6 Pin stress combinations 24 6.6.1 Pin stress combination c
34、ategorization 24 6.6.2 Non-supply and supply to supply combinations (1, 2, N) 26 6.6.3 Non-supply to non-supply combinations . 27 6.7 HBM stressing with a low-parasitic simulator . 28 6.7.1 Low-parasitic HBM simulator . 28 6.7.2 Requirements for low parasitics . 28 6.8 Testing after stressing 28 7 F
35、ailure criteria . 28 8 Component classification . 28 Annex A (informative) HBM test method flow chart . 30 Annex B (informative) HBM test equipment parasitic properties . 33 B.1 Optional trailing pulse detection equipment / apparatus 33 B.2 Optional pre-pulse voltage rise test equipment 34 B.3 Open-
36、relay tester capacitance parasitics . 36 B.4 Test to determine if an HBM simulator is a low-parasitic simulator 36 Annex C (informative) Example of testing a product using Table 2, Table 3, or Table 2 with a two-pin HBM tester 38 C.1 General . 38 C.2 Procedure A (following Table 2): . 39 C.3 Alterna
37、tive procedure B (following Table 3): 40 C.4 Alternative procedure C (following Table 2): 41 Annex D (informative) Examples of coupled non-supply pin pairs . 43 Annex E (normative) Cloned non-supply (I/O) pin sampling test method 44 E.1 Purpose and overview . 44 E.2 Pin sampling overview and statist
38、ical details . 44 E.3 IC product selections 45 E.4 Randomly selecting and testing cloned I/O pins 46 E.5 Determining if sampling can be used with the supplied Excel spreadsheet 46 E.5.1 Using the supplied Excel spreadsheet . 46 E.5.2 Without using the Excel spreadsheet . 46 E.6 HBM testing with a sa
39、mple of cloned I/O pins . 46 E.7 Examples of testing with sampled cloned I/Os . 47 Bibliography 50 Figure 1 Simplified HBM simulator circuit with loads 12 Figure 2 Current waveform through shorting wires . 15 Figure 3 Current waveform through a 500 resistor 16 Figure 4 Peak current short circuit rin
40、ging waveform 17 Figure A.1 HBM test method flow chart (1 of 3) 30 Figure B.1 Diagram of trailing pulse measurement setup 33 Figure B.2 Positive stress at 4 000 V . 34 Figure B.3 Negative stress at 4 000 V 34 BS EN IEC 60749-26:2018IEC 60749-26:2018 IEC 2018 3 6.5 Pin groupings 24 6.5.1 Supply pin g
41、roups 24 6.5.2 Shorted non-supply pin groups 24 6.6 Pin stress combinations 24 6.6.1 Pin stress combination categorization 24 6.6.2 Non-supply and supply to supply combinations (1, 2, N) 26 6.6.3 Non-supply to non-supply combinations . 27 6.7 HBM stressing with a low-parasitic simulator . 28 6.7.1 L
42、ow-parasitic HBM simulator . 28 6.7.2 Requirements for low parasitics . 28 6.8 Testing after stressing 28 7 Failure criteria . 28 8 Component classification . 28 Annex A (informative) HBM test method flow chart . 30 Annex B (informative) HBM test equipment parasitic properties . 33 B.1 Optional trai
43、ling pulse detection equipment / apparatus 33 B.2 Optional pre-pulse voltage rise test equipment 34 B.3 Open-relay tester capacitance parasitics . 36 B.4 Test to determine if an HBM simulator is a low-parasitic simulator 36 Annex C (informative) Example of testing a product using Table 2, Table 3, o
44、r Table 2 with a two-pin HBM tester 38 C.1 General . 38 C.2 Procedure A (following Table 2): . 39 C.3 Alternative procedure B (following Table 3): 40 C.4 Alternative procedure C (following Table 2): 41 Annex D (informative) Examples of coupled non-supply pin pairs . 43 Annex E (normative) Cloned non
45、-supply (I/O) pin sampling test method 44 E.1 Purpose and overview . 44 E.2 Pin sampling overview and statistical details . 44 E.3 IC product selections 45 E.4 Randomly selecting and testing cloned I/O pins 46 E.5 Determining if sampling can be used with the supplied Excel spreadsheet 46 E.5.1 Using
46、 the supplied Excel spreadsheet . 46 E.5.2 Without using the Excel spreadsheet . 46 E.6 HBM testing with a sample of cloned I/O pins . 46 E.7 Examples of testing with sampled cloned I/Os . 47 Bibliography 50 Figure 1 Simplified HBM simulator circuit with loads 12 Figure 2 Current waveform through sh
47、orting wires . 15 Figure 3 Current waveform through a 500 resistor 16 Figure 4 Peak current short circuit ringing waveform 17 Figure A.1 HBM test method flow chart (1 of 3) 30 Figure B.1 Diagram of trailing pulse measurement setup 33 Figure B.2 Positive stress at 4 000 V . 34 Figure B.3 Negative str
48、ess at 4 000 V 34 4 IEC 60749-26:2018 IEC 2018 Figure B.4 Illustration of measuring voltage before HBM pulse with a Zener diode or a device 35 Figure B.5 Example of voltage rise before the HBM current pulse across a 9,4 V Zener diode 35 Figure B.6 Diagram of a 10-pin shorting test device showing cur
49、rent probe 37 Figure C.1 Example to demonstrate the idea of the partitioned test 38 Figure E.1 SPL, V1, VM, and z with the Bell shape distribution pin failure curve 45 Figure E.2 I/O sampling test method flow chart 49 Table 1 Waveform specification . 19 Table 2 Preferred pin combinations sets 25 Table 3 Alternative pin combinations sets 26 Table 4 HBM ESD component classification levels . 29 Table C.1 Product testing in accordance with Table 2 40 Table
