1、BSI Standards Publication Device embedded substrate Part 2-1: Guidelines General description of technology PD IEC/TS 62878-2-1:2015National foreword This Published Document is the UK implementation of IEC/TS 62878-2-1:2015. The UK participation in its preparation was entrusted to Technical Committee
2、 EPL/501, Electronic Assembly Technology. A list of organizations represented on this committee can be obtained on request to its secretary. This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. The British Standar
3、ds Institution 2015. Published by BSI Standards Limited 2015 ISBN 978 0 580 82120 2 ICS 31.180; 31.190 Compliance with a British Standard cannot confer immunity from legal obligations. This Published Document was published under the authority of the Standards Policy and Strategy Committee on 30 Apri
4、l 2015. Amendments/corrigenda issued since publication Date Text affected PUBLISHED DOCUMENT PD IEC/TS 62878-2-1:2015 IEC TS 62878-2-1 Edition 1.0 2015-03 TECHNICAL SPECIFICATION SPECIFICATION TECHNIQUE Device embedded substrate Part 2-1: Guidelines General description of technology Substrat avec ap
5、pareil(s) intgr(s) Partie 2-1: Directives Description gnrale de la technologie INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE ICS 31.180; 31.190 ISBN 978-2-8322-2434-2 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commi
6、ssion Electrotechnique Internationale Warning! Make sure that you obtained this publication from an authorized distributor. Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agr. colour inside PD IEC/TS 62878-2-1:2015 2 IEC TS 62878-2-1:2015 IEC 2015 CONTENT
7、S FOREWORD . 4 INTRODUCTION . 6 1 Scope 7 2 Normative references. 7 3 Terms, definitions and abbreviations 7 3.1 Terms and definitions 7 3.2 Abbreviations 7 4 Technology of device embedded substrate . 7 4.1 Basic structures 7 4.2 Technology of device embedded substrate 9 4.3 Structures of device emb
8、edded substrates and terms used in this specification. 12 5 Jisso mounting and interconnection 13 5.1 General . 13 5.2 Interconnections and structures of device embedded substrate 15 5.3 Device embedding by conventional process . 17 5.4 Device embedding using vias 19 6 Naming of each section . 22 6.
9、1 General . 22 6.2 General definition of top and bottom surfaces 22 6.3 Naming of layers and interconnection position . 24 6.4 Definitions of insulation layer thickness, conductor gap and connection distance between terminal and conductor 27 General . 27 6.4.1Insulation layer thickness, conductor ga
10、p and electrode/conductor gap in 6.4.2 pad connection 27 Insulation layer thickness, conductor gap and electrode/conductor gap in 6.4.3 a via connection . 28 6.5 Additional information 28 Additional information for the insulation layer 28 6.5.1Additional information for conductor gap and electrode/c
11、onductor gap . 29 6.5.2 Bibliography . 30 Figure 1 Examples of device embedded substrate 8 Figure 2 Completed device embedded substrate (pad connection) 9 Figure 3 Completed device embedded substrate (via connection) . 9 Figure 4 Structure of a pad connection type substrate on a passive device embed
12、ded ceramics base 10 Figure 5 Structure of a device embedded substrate using a ceramic board as the base (via connection type) . 10 Figure 6 Entire structure of device embedded substrate 15 Figure 7 Base (typical structure) . 16 Figure 8 Base (cavity structure) 16 Figure 9 Base (insulator) 16 PD IEC
13、/TS 62878-2-1:2015 3 IEC TS 62878-2-1:2015 IEC 2015 Figure 10 Base (Conductive carrier metal plate). 16 Figure 11 Passive device embedded ceramic board used as a base 17 Figure 12 Ceramic board used as base (ceramic) . 17 Figure 13 Wire bonding connection and embedding of active device bare die 17 F
14、igure 14 Soldering connection and embedding of active device . 18 Figure 15 Soldering connection of square type passive device 18 Figure 16 Conductive resin connection and embedding of active device 18 Figure 17 Conductive resin connection and embedding of square type passive device . 19 Figure 18 S
15、oldering connection into through hole and embedding of passive device 19 Figure 19 Connection by copper plating after embedding of active device . 19 Figure 20 Connection by copper plating after embedding of square type passive device 20 Figure 21 Conductive paste connection after embedding of activ
16、e device package 20 Figure 22 Conductive paste connection after embedding of square type passive device chip 20 Figure 23 Device embedded substrate for device embedding in multi-layers 21 Figure 24 Embedding of devices over multiple layers 21 Figure 25 Resin base substrate 21 Figure 26 Conductor and
17、 metal sheet/copper foil as base substrate 22 Figure 27 Device embedded substrate using passive device embedded ceramic substrates as base substrate Second type 22 Figure 28 Definition of top and bottom surfaces 23 Figure 29 Definition of top and bottom surfaces (mounting of a mother board) . 23 Fig
18、ure 30 Names of layers in pad connection 24 Figure 31 Additional information concerning the interconnection position 25 Figure 32 Names of layers in via connection I . 25 Figure 33 Names of layers in via connection II 26 Figure 34 Names of layers in via connection III . 26 Figure 35 Definition of in
19、sulating layer thickness and conductor gap in pad connection28 Figure 36 Definition of electrode gap in via connection . 28 Figure 37 Additional illustration of insulating layer thickness . 29 Figure 38 Additional illustration for conductor gap and electrode/connector gap 29 Table 1 Classification o
20、f device embedding 11 Table 2 Formed embedded device into the substrate 12 Table 3 Embedded device structure and fabrication process . 13 Table 4 Jisso mounting and interconnection of device embedded substrate . 14 Table 5 Names of layers of device embedded board . 27 PD IEC/TS 62878-2-1:2015 4 IEC
21、TS 62878-2-1:2015 IEC 2015 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ DEVICE EMBEDDED SUBSTRATE Part 2-1: Guidelines General description of technology FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechn
22、ical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
23、 Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, gov
24、ernmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions
25、 or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Publications have the form of recommendations for internatio
26、nal use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order t
27、o promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly
28、 indicated in the latter. 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any services carried out by independent certification bodi
29、es. 6) All users should ensure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property
30、 damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this
31、 publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or
32、all such patent rights. The main task of IEC technical committees is to prepare International Standards. In exceptional circumstances, a technical committee may propose the publication of a Technical Specification when the required support cannot be obtained for the publication of an International S
33、tandard, despite repeated efforts, or the subject is still under technical development or where, for any other reason, there is the future but no immediate possibility of an agreement on an International Standard. Technical Specifications are subject to review within three years of publication to de
34、cide whether they can be transformed into International Standards. IEC TS 62878-2-1, which is a Technical Specification, has been prepared by IEC technical committee 91: Electronics assembly technology. PD IEC/TS 62878-2-1:2015 5 IEC TS 62878-2-1:2015 IEC 2015 The text of this Technical Specificatio
35、n is based on the following documents: Enquiry draft Report on voting 91/1142/DTS 91/1163A/RVC Full information on the voting for the approval of this Technical Specification can be found in the report on voting indicated in the above table. A list of all parts in the IEC 62878 series, published und
36、er the general title Device embedded substrate, can be found on the IEC website. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC we
37、bsite under “http:/webstore.iec.ch“ in the data related to the specific publication. At this date, the publication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. IMPORTANT The colour inside logo on the cover page of this publication indicates that it contains colours whic
38、h are considered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer. PD IEC/TS 62878-2-1:2015 6 IEC TS 62878-2-1:2015 IEC 2015 INTRODUCTION This part of IEC 62878 provides guidance with respect to device embedded substrate, f
39、abricated by embedding discrete active and passive electronic devices into one or multiple inner layers of a substrate with electric connections by means of vias, conductor plating, conductive paste, and printing. Within the IEC 62878 series, IEC 62878-1-1 specifies the test methods, IEC TS 62878-2-
40、1 gives a general description of the technology, IEC TS 62878-2-3 provides guidance on design, and IEC TS 62878-2-4 specifies the test element groups. The device embedded substrate may be used as a substrate to mount SMDs to form electronic circuits, as conductor and insulator layers may be formed a
41、fter embedding electronic devices. The purpose of the IEC 62878 series is to achieve a common understanding with respect to structures, test methods, design and fabrication processes and the use of the device embedded substrate in industry. PD IEC/TS 62878-2-1:2015 7 IEC TS 62878-2-1:2015 IEC 2015 D
42、EVICE EMBEDDED SUBSTRATE Part 2-1: Guidelines General description of technology 1 Scope This part of IEC 62878 describes the basics of device embedding substrate. This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example
43、active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components. The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421. 2 Normativ
44、e references The following documents, in whole or in part, are normatively referenced in this document and are indispensable for its application. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) app
45、lies. IEC 60194, Printed board design, manufacture and assembly Terms and definitions IEC 61189 (all parts), Test methods for electrical materials, printed boards and other interconnection structures and assemblies 3 Terms, definitions and abbreviations 3.1 Terms and definitions For the purposes of
46、this document, the terms and definitions given in IEC 60194 apply. 3.2 Abbreviations BGA ball grid array I/O in/out IPD integrated passive device LGA land grid array LTCC low temperature co-fired ceramic MEMS micro electro mechanical systems PoP package on package QFN quad flat no-lead package QFP q
47、uad flat package SMD surface mount device SOJ small outline J-leaded package WLP wafer level package 4 Technology of device embedded substrate 4.1 Basic structures Figure 1 shows an example of device embedding structures in the fabrication process of a device embedded substrate. Active and passive d
48、evices are connected to each other by interlayer vias and/or conductor patterns. Insulating layers are formed using insulating materials PD IEC/TS 62878-2-1:2015 8 IEC TS 62878-2-1:2015 IEC 2015 with vias for connection of inside conductor patterns to the conductor patterns formed on the surface(s)
49、of the substrate. Figure 2 shows the substrate with connections using pads. Figure 3 shows the board using via connections. The insulating layer includes rigid and flexible insulating resins such as phenol resin, epoxy resin, polyimide resin and modified polyimide resin, which may be reinforced with glass cloth, aramid cloth or paper. Interconnections include conventional interconnect
