1、 BACKPLANE DATA BUSARINC SPECIFICATION 659PUBLISHED: DECEMBER 27, 1993AN DOCUMENTPrepared byAIRLINES ELECTRONIC ENGINEERING COMMITTEEPublished byAERONAUTICAL RADIO, INC.2551 RIVA ROAD, ANNAPOLIS, MARYLAND 21401This document is based on material submitted by variousparticipants during the drafting pr
2、ocess. Neither AEEC norARINC has made any determination whether these materialscould be subject to claims of patent or other proprietary rights bythird parties, and no representation or warranty, express orimplied, is made in this regard. Any use of or reliance on thisdocument shall constitute an ac
3、ceptance hereof “as is“ and besubject to this disclaimer.Honeywell, Inc. is a known holder of patents that apply toARINC Specification 659. Parties involved with designingequipment to meet this standard are advised that it may benecessary to license the associated technologies through:Corporate Pate
4、nt OfficeHoneywell, Inc.P. O. Box 21111Phoenix, AZ 85036-1111Copyright 1993 byAERONAUTICAL RADIO, INC.2551 Riva RoadAnnapolis, Maryland 21401-7465 USAARINC SPECIFICATION 659BACKPLANE DATA BUSPublished: December 27, 1993Prepared by the Airlines Electronic Engineering CommitteeSpecification 659 Adopte
5、d by the Airlines Electronic Engineering Committee: October 20, 1993Specification 659 Adopted by the Industry: December 27, 1993ARINC SPECIFICATION 659TABLE OF CONTENTSITEM SUBJECT PAGE1.0 INTRODUCTION 11.1 Purpose of Document 11.2 Document Scope 11.3 Relationship to Other Standards 11.3.1 Other Dat
6、a Bus Standards 11.3.2 IMA Packaging Standards 11.4 ARINC Specification 659 Basic Philosophy 11.5 ARINC Specification 659 Overview 11.6 Support of ARINC Report 651 11.7 Environmental Factors 21.8 Specification Language and Terminology 21.9 Related Documents 22.0 TECHNICAL DESCRIPTION 32.1 Basic Arch
7、itecture 32.2 Physical Layer 32.3 Data Link Layer 32.3.1 Media Access Control (MAC) Sub-Layer 32.3.2 Logical Link Control (LLC) Sub-Layer 42.4 Data Types 42.5 Table Compatibility 42.6 Error Management 42.6.1 Fault Detection 42.6.2 Fault Tolerance 42.6.3 Data Reliability Modes 42.7 Test and Maintenan
8、ce 42.7.1 Table Load Path 52.7.2 Test Path 53.0 PHYSICAL LAYER 63.1 Overview 63.2 Interface Signal Description 63.2.1 Data Lines 63.2.2 Clock Lines 63.2.3 Transceiver Power Input Lines 63.2.4 Test Bus 63.2.4.1 Data and Control 63.2.4.2 Clock 63.2.4.3 Bandgap Ground Reference 63.2.4.4 Terminator Volt
9、age 63.2.5 Terminator Voltage Lines 63.2.6 Slot Identification Pins 73.2.7 Power Source Pins 73.2.8 Bandgap Ground Reference Pins 73.3 Electrical Performance Characteristics 73.3.1 Bus Data and Clock Line Requirements 73.3.2 Module Data and Clock Line DC Requirements 73.3.3 Bus Data and Clock Line A
10、C Requirements 83.3.3.1 Module Data Line Inputs 83.3.3.2 Signal and Enable Outputs 93.3.4 Signal Pair State Definitions 93.3.5 Clock Accuracy 93.4 Transceivers 93.5 Bus Encoding 93.6 Physical Separation 103.6.1 BIU Separation 103.6.2 Bus Power Suppy Separation 103.6.3 Bus Line Separation Requirement
11、s 103.7 Passive Terminator 113.8 LRM Identification 113.9 Connector Pin Assignments 113.10 Power Supply Routing 113.11 Bus Media 11iiARINC SPECIFICATION 659TABLE OF CONTENTSITEM SUBJECT PAGE3.11.1 Printed Circuit Board (PCB) 113.11.2 Wire 114.0 DATA LINK LAYER 124.1 Bus Operation Overview 124.1.1 Wi
12、ndow Structure 124.1.2 Frame Organization 124.1.3 BIU State Description 134.1.4 Programmable Register Definitions 134.1.4.1 Full-resolution Time Register 134.1.4.1.1 Time Register 134.1.4.1.2 Time Prescale Count Register 134.1.4.2 Version Register 134.1.4.2.1 Table Major Version Field 144.1.4.2.2 Ta
13、ble Minor Version Field 144.1.4.2.3 Cabinet Position Field 144.1.4.3 Frame Change Enable 144.1.5 Operational Constants 144.1.5.1 Gap Size 144.1.5.2 Master/Shadow Step Size ()154.1.5.3 Initial Sync Wait Limit 154.1.5.4 Time Scaling Factor 164.2 Synchronization 164.2.1 Frame-level Synchronization 164.
14、2.2 Bit-level Synchronization 164.2.2.1 Resync Pulse Operation 164.2.2.2 BIU-to-BIU Skew Limits 174.2.2.2.1 Skew Definitions 174.2.2.2.2 Skew Relationships 184.2.2.2.3 Total Skew Requirements 184.2.2.3 Master/Shadow Step Size Selection 194.2.3 Loss of Synchronization 194.2.3.1 Unexpected Resync Puls
15、e 194.2.3.2 Wrong Resync Type 204.2.3.3 Resync Code Miscompare 204.2.3.4 Version Code Miscompare 204.2.3.5 Uncorrectable Data during Frame Change 204.2.3.6 Init Sync Pulse 204.2.3.7 Transciever Enable Mismatch 204.2.4 Full-resolution Time Register Operation 204.3 Message Operation 204.3.1 Basic Mess
16、age Operation 214.3.1.1 Basic Message Structure 214.3.1.2 Basic Message Transmit 214.3.1.3 Basic Message Receive 214.3.1.4 Basic Message Skip 224.3.2 Master/Shadow Message Operation 224.3.2.1 Master/Shadow Message Structure 224.3.2.1.1 Bidirectional Master/Shadow Messages 224.3.2.2 Master/Shadow Mes
17、sage Transmit 224.3.2.3 Master/Shadow Message Receive 234.3.2.4 Master/Shadow Message Skip 234.3.3 Implicit Idle 234.3.4 Initial Sync Message Operation 234.3.4.1 Initial Sync Message Structure 244.3.4.2 Initial Sync Message Transmit 244.3.4.3 Initial Sync Message Receive 244.3.5 Short Resync Message
18、 Operation 254.3.5.1 Short Resync Message Structure 254.3.5.2 Short Resync Message Transmit/Receive 254.3.6 Long Resync Message Operation 254.3.6.1 Long Resync Message Structure 264.3.6.2 Long Resync Message Transmit 26iiiARINC SPECIFICATION 659TABLE OF CONTENTSITEM SUBJECT PAGE4.3.6.3 Long Resync M
19、essage Receive 274.3.6.3.1 In Sync BIU Operation 274.3.6.3.2 Out-of-Sync BIU Operaton 284.3.6.4 Entry Resync Message Operation 294.3.6.4.1 Entry Resync Transmit 294.3.6.4.2 Entry Resync Receive 294.3.6.4.3 Entry Resync Message Frequency 304.3.6.5 Frame Change Message Operation 304.3.6.5.1 Frame Chan
20、ge Message Transmit 304.3.6.5.2 Frame Change Message Receive 304.3.7 Transceiver Enable Assertion 304.3.8 Transceiver Enable Monitoring 314.4 Receive Data Selection 314.5 Basic Services at BIU/Host Interface 324.5.1 Data Transmission Services 324.5.1.1 Data Transmit Requests 324.5.1.1.1 Function 324
21、.5.1.1.2 Parameters 324.5.1.1.3 Activation 324.5.1.2 Data Transmit Confirmation 324.5.1.2.1 Function 324.5.1.2.2 Parameters 334.5.1.2.3 Access to Service 334.5.2 Data Reception Services 334.5.2.1 Data Receive Indication 334.5.2.1.1 Function 334.5.2.1.2 Parameters 334.5.2.1.3 Access to Service 334.5.
22、3 Frame Change Services 334.5.3.1 Frame Change Enable 334.5.3.1.1 Function 334.5.3.1.2 Parameters 334.5.3.1.3 Activation 334.5.3.2 Frame Change Receive Indication 334.5.3.2.1 Function 334.5.3.2.2 Parameters 334.5.3.2.3 Access to Service 344.5.4 Time Register Access Service 344.5.4.1 Time Register Re
23、ad 344.5.4.1.1 Function 344.5.4.1.2 Parameters 344.5.4.1.3 Access to Service 344.5.5 Global Error Report Services 344.5.5.1 BIU State Indication 344.5.1.1.1 Function 344.5.5.1.2 Parameters 344.5.5.1.3 Access to Service 344.5.5.2 Error Indication 344.5.5.2.1 Function 344.5.5.2.2 Parameters 344.5.5.2.
24、3 Access to Service 344.5.6 Control of the BIU by the Host 344.5.6.1 Activation of BIU in Operational Mode 344.5.6.1.1 Function 344.5.6.1.2 Parameters 344.5.6.1.3 Activation 354.5.6.2 BIU Shutdown 354.5.6.2.1 Function 354.5.6.2.2 Parameters 354.5.6.2.3 Activation 35ivARINC SPECIFICATION 659TABLE OF
25、CONTENTSITEM SUBJECT PAGEATTACHMENTS1 Glossary 36-372-1 IMA Cabinet Backplane Architecture 382-2 Nomenclature 392-3 Frame Description Language 40-563-1 Interface Block Diagram 573-2 Interface Signal Names 583-3 Backplane Logic Levels 593-4 Set-Up and Hold Timing 603-5 Data/Clock Skew Measurement Poi
26、nts 613-6 Signal Output Test Circuit 623-7 Bus Encoding Example 633-8 Backplane Terminator Structure 643-9 Insert Pin Assignment for ARINC 650 65-67Size 1 Connector3-10 Insert Pin Assignment for ARINC 650 68-69Size 2 Connector3-11 Power Supply Routing 724-1 Backplane Activity 734-2 Window Definition
27、 Taxonomy 744-3 Initial Frame Definition 75-814-4 Example Frame Organization 824-5 Window Commands 834-6 BIU State Transition Diagram 844-7 Full-Resolution Timer Behavior 854-8 Version Register Components 864-9 Frame Level Synchronization Flow Diagram 874-10 Bit-Level Resync Pulse Timing Example 884
28、-11 Spatial Skew Measurement Points 894-12 Temporal Skew Measurement Points 904-13 XY Skew Measurement Points 914-14 Temporal Resync Inaccuracy Measurement 924-15 XY Resync Inaccuracy Measurement 934-16 Delta () Timing Considerations 944-17 Full-Resolution Time Register Components 954-18 Basic Messa
29、ge Structure 964-19 Master/Shadow Message Structure(a) Master Transmits 97(b) Shadow 1 Transmits 97(c) Shadow 2 Transmits 98(d) Shadow 3 Transmits 984-20 Initial Sync Message Structure 994-21 Short Resync Message Structure 1004-22 Long Resync Message Structure(a) Master 101(b) Third Shadow 1024-23 S
30、ync Behavior for Long Resync Messages 103-1044-24 Out_of_Sync Behavior for Long Resync Messages 105-1064-25 Data Validation Tables 107-118APPENDICESA Debug Features 119-124vARINC SPECIFICATION 659 - Page 11.0 INTRODUCTION1.1 Purpose of DocumentThis document defines a standard for transfer of digital
31、data between Line Replaceable Modules (LRMs) within anIntegrated Modular Avionics (IMA) cabinet. Thisspecification defines the characteristics necessary tointerface with a general purpose backplane data bus forintra-cabinet communication. It defines the electricalcharacteristics and behavior expecte
32、d of the LRM and thebackplane where they meet at the LRM to backplaneconnectors.1.2 Document ScopeThis document defines the electrical characteristics for acontrolled impedance backplane bus for use withIntegrated Modular Avionics (IMA). It defines thenecessary characteristics of the bus that will e
33、nsureelectrical compatibility at the interface between theavionics module and the IMA cabinet. ARINCSpecification 659 defines the protocol, timing, bit rate andpower requirements for the physical backplane. It definesthe physical medium, physical layer and parts of theMedia Access Control (MAC) subl
34、ayer referred to in theOSI Reference Model.1.3 Relationship to Other Standards1.3.1 Other Data Bus StandardsARINC Specification 659 is intended to address intra-cabinet communications between LRMs within a cabinetconforming to ARINC Report 651. ARINC Specification659 satisfies unique IMA requirement
35、s for medium/highthroughput of data, strict fault isolation, and data transferdeterminism.ARINC Specification 659 addresses internal cabinetcommunications, thus complementing ARINCSpecifications 429, 629, 636, and 646, which addressexternal cabinet communications.1.3.2 IMA Packaging StandardsARINC 6
36、50 defines the physical-mechanical andenvironmental characteristics of an IMA cabinet. Thephysical-electrical characteristics defined in this documentare compatible with the worst case requirements permittedby ARINC 650 regarding the length of backplanetransmission data and the number and spacing of
37、backplane module connections.This document also details the specific pin allocations forthe ARINC 650 backplane connector field dedicated tointra-cabinet data transfer.1.4 ARINC Specification 659 Basic PhilosophyARINC Specification 659 defines a backplane datacommunication protocol which allows stan
38、dard avionicsLRMs to transmit and receive digital data within acommon cabinet. The concepts for this cabinet aredescribed by ARINC Report 651, “Design Guidance forIntegrated Modular Avionics (IMA)“.The IMA concepts include the use of common resourcesshared among several functions within a cabinet. T
39、hesefunctions may be separated into independent partitions.To preserve the independence, it is imperative that nopartition adversely affect another partition, no matter howfaulty its design or behavior. This is called robustpartitioning. In particular, the access to shared resourcesmust not deviate
40、in any way from its designed allocation(even if IMA components are faulty). This is calleddeterminism.The backplane bus is a key shared resource. ARINCSpecification 659 provides for its determinism through theuse of the Table Driven Proportional Access (TDPA)protocol. It also enforces elements of ro
41、bust partitioningamong the LRMs it serves.To support the operational goals of the IMA cabinet, thebackplane bus must provide a high level of reliability andfault tolerance. Reliability is realized through minimizationof logic and bus lines. Fault tolerance, defined as theability to provide a needed
42、function and to continueoperation in a specified manner after one or more faultshave occurred, is provided through high coverage faultdetection, fault containment, and redundancy.1.5 ARINC Specification 659 OverviewThis document is organized into four sections, fourattachments, and an appendix.Secti
43、on 1 provides this introduction and general overviewof ARINC Specification 659, and points out relatedARINC documents.Section 2 provides a technical overview of ARINCSpecification 659. Basic architecture, robust partitioning,supported data types and error management features of thebus are described.
44、Section 3 provides detailed implementation description ofthe bus physical layer. This includes mechanical,electrical, and data line definition.Section 4 provides detailed description of the datatransfer protocol, including data format, operation duringsynchronization and loss of synchronization, ini
45、tialization,and error handling.Attachment 1 is the glossary. Attachments 2 through 4provide figures and other amplifying material for sections2 through 4, respectively.Appendix A describes the bus debug feature.1.6 Support of ARINC Report 651Many of the goals and objectives of ARINC Report 651are em
46、bodied in the backplane bus. The specificobjectives are broad in scope. Some of the salientfeatures of ARINC Specification 659 which supportARINC Report 651 are listed below:Support of robust partitioning, enabling reliablecontrol of shared resourcesARINC SPECIFICATION 659 - Page 21.0 INTRODUCTION (
47、contd)1.6 Support of ARINC Report 651 (contd)High reliability to support operational safetyHigh data availability, ultimately resulting in efficientaircraft operationFault tolerance, supporting deferred maintenancegoals through extended mean-time betweenmaintenance alert/action (MTBMA)Minimal comple
48、xity, increasing system reliability anddecreasing spares unit costsDeterministic operation, aiding in certification offunctions and the IMA itselfFlexibility of subsystem design, reducing LRM costthrough the ability to accommodate variationsNo constraint for any LRM to be connected to anyparticular
49、slot of a cabinet.There may be additional features which support the goalsand objectives of IMA not listed above.1.7 Environmental FactorsThe bus designed to meet the standards contained hereinshould comply with the pertinent RTCA DocumentDO-160, “Environmental Conditions and Test Proceduresfor Airborne Equipment“ and other appropriate airframeand regulatory agency documents.1.8 Specification Language and TerminologyThe tight coupling inherent in backplane buses requireslanguage more stringent than has historically been used inAEEC documents.Attachment 1 is a glossary of terms used i
