1、BRITISH STANDARD BS CECC 90104:1981 Incorporating Amendment Nos. 1 and 2 Specification for Harmonized system of quality assessment for electronic components Family specification C. Mos Digital Integrated Circuits Series 4000B and 4000UBBS CECC90104:1981 BSI 03-2000 ISBN 0 580 35805 4 Amendments issu
2、ed since publication Amd. No. Date of issue Comments 5197 August 1986 5597 April 1987 Indicated by a sideline in the marginBS CECC90104:1981 BSI 03-2000 i Contents Page National foreword ii Foreword iii Text of CECC 90104 1BS CECC90104:1981 ii BSI 03-2000 National foreword This British Standard has
3、been prepared under the direction of the Electronic Components Standards Committee. It is identical with CENELEC Electronic Components Committee (CECC) 90104 Family specification: C.MOS Digital integrated circuits Series 4000 B and 4000 UB. This standard is a harmonized specification within the CECC
4、 system. Terminology and conventions. The text of the CECC specification has been accepted as suitable for publication, without deviation, as a British Standard. Certain terminology and conventions are used, however, that are not identical with those used in British Standards. Attention is particula
5、rly drawn to the following. The comma has been used throughout as a decimal maker. In British Standards it is current practice to use a full point on the baseline as the decimal marker. Cross references. The British Standard harmonized with CECC00100 is BSE9000 “General requirements for electronic c
6、omponents of assessed quality harmonized with the CENELEC Electronic Components Committee System” Part 1 “Basic rules”. The following International Standards are referred to in the text and for each there is a corresponding British Standard; these are listed below. Scope. This Standard lists the gen
7、eral information for ratings, characteristics and inspection requirements for a series of integrated circuits which shall be included as mandatory requirements in detail specifications in accordance with BS CECC90000. Detail specification layout. In the event of conflict between the requirements of
8、this specification and the provisions of Section3 of BS9000-2 the latter shall take precedence except the front page layout will be in accordance with BS9000 Circular Letter No.15. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards a
9、re responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. International Standard Corresponding British Standard CECC 90000:1976 BS CECC 90000:1977 Harmonized system of quality assessment for electronic components: Gene
10、ric specification: monolithic integrated circuits (Identical) CECC 90100:1976 BS CECC 90100:1977 Harmonized system of quality assessment for electronic components: Sectional specification: Digital monolithic integrated circuits (Identical) IEC 191-2:1966 BS 3934:1965 Dimensions of semiconductor devi
11、ces (Related) Summary of pages This document comprises a front cover, an inside front cover, pagesi andii, the CECC title page, pagesiitoiv, pages 1 to 13 and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the ame
12、ndment table on the inside front cover.BS CECC90104:1981 ii BSI 03-2000 Content Page Foreword iii 1 Limiting conditions of use for the family 1 2 Recommended conditions of use and associated characteristics for the family 2 3 Inspection requirements 8BS CECC90104:1981 BSI 03-2000 iii Foreword The CE
13、NELEC Electronic Components Committee (CECC) is composed of those member countries of the European Committee for Electrotechnical Standardization (CENELEC) who wish to take part in a harmonized System for electronic components of assessed quality. The object of the System is to facilitate internatio
14、nal trade by the harmonization of specifications and quality assessment procedures for electronic components, and by the grant of an internationally recognized Mark or Certificate, of Conformity. The components produced under the System are thereby accepted by all member countries without further te
15、sting. This document has been formally approved by the CECC and has been prepared for those countries taking part in the System who wish to prepare and issue detail specifications for DIGITAL INTEGRATED CIRCUITS. It should be read in conjunction with document CECC 00100: Basic Rules (1974). At the d
16、ate of printing of this document the member countries of the CECC are Belgium, Denmark, France, Germany, Ireland, Italy, the Netherlands, Norway, Sweden, Switzerland, the United Kingdom, and copies of it can be obtained from the addressees shown on the inside cover. Preface This family specification
17、 was prepared by CECC Working Group9: Integrated Circuits. It contains the general information for the C.MOS series4000B and4000UB. Together with the device type detail specification, usually prepared nationally, it forms the complete detail specification for the device belonging to series4000B or40
18、00UB. The text of this specification was circulated to the CECC for voting in the documents listed below and was ratified by the CECC for printing as a CECC specification. Document Voting Date Report on the Voting CECC(Secretariat)833 November 1979 CECC(Secretariat)914iv blankBS CECC90104:1981 BSI 0
19、3-2000 1 page of 1 13 CECC 90104-xxx Date of issue ELECTRONIC COMPONENT OF ASSESSED QUALITY IN ACCORDANCE WITH CECC 90000: Generic specification: monolithic integrated circuits, and CECC 90100: Sectional specification, digital monolithic integrated circuits FAMILY SPECIFICATION for C.MOS 4000 B and
20、4000 UB series (digital devices) TYPICAL CONSTRUCTION: Silicon complementary MOS, buffered (B) and unbuffered (UB) outputs, cavity and non cavity packages. CAUTION: THESE ARE STATIC SENSITIVE DEVICES Outline and dimensions: In accordance with IEC Publication 191-2 See detail specification for specif
21、ic type Assessment levels: R, S, T and V Terminal connections, lead plating and material: See detail specification for specific type 1 Limiting conditions of use for the family (not for inspection purposes) 1.1 Maximum supply voltage, positive V DD= + 18 V 1.2 Maximum supply voltage, negative V DD=
22、0,5 V 1.3 Maximum positive input voltage V I= V DD+ 0,5 V See Note 1 1.4 Maximum negative input voltage V I= 0,5 V 1.5 Maximum power dissipation per output and per package See detail specification 1.6 Maximum continuous current (any input) |I| = 10 mA 1.7 Maximum continuous current into any output S
23、ee detail specification NOTE 1Except for transient (See 1.10 and 2.14.2) See the relevant Qualified Products List (QPL) for availability of components qualified to this specification BS CECC90104:1981 2 BSI 03-2000 2 Recommended conditions of use and associated characteristics for the family (not fo
24、r inspection purposes) These apply over the operating temperature range, unless otherwise stated. All voltages are referenced toV SS 1.8 Operating temperature range T amb Full = 55 to + 125 C Limited = 40 to+ 85 C 1.9 Storage temperature range T stg 65 to + 150 C 1.10 Transient energy rating See det
25、ail specification Symbol V DD (V) T amb= T amb min.T amb= + 25 C T amb= T amb max.Unit 2.1 Quiescent device current V IL= 0V, V IH= V DD 2.1.1 For full operating temperature range a Gates 5 10 15 0,25 0,5 1 0,25 0,5 1 7,5 15 30 Buffers, flip-flops 5 10 15 1 2 4 1 2 4 30 60 120 MSI 5 10 15 5 10 20 5
26、10 20 150 300 600 LSI I DDA 5 10 15 15 25 50 15 25 50 375 750 1 500 4A 2.1.2 For limited operating temperature range a Gates 5 10 15 1 2 4 1 2 4 7,5 15 30 Buffers, flip-flops 5 10 15 4 8 16 4 8 16 30 60 120 MSI 5 10 15 20 40 80 20 40 80 150 300 600 LSI 5 10 15 50 100 200 50 100 200 375 750 1500 a Th
27、e Detail Specification shall specify the applicable groupBS CECC90104:1981 BSI 03-2000 3 Symbol V DD (V) T amb= T amb min.T amb= + 25 C T amb= T amb max.Unit 2.2 Low level output voltage V IL= 0V, V IH= V DD|I 0 | 1 4A V OLA 5 10 15 0,05 0,05 0,05 0,05 0,05 0,05 0,05 0,05 0,05 V 2.3 High level outpu
28、t voltage V IL= 0 V, V IH= V DD|I 0 | 1 4A V OHB 5 10 15 4,95 9,95 14,95 4,95 9,95 14,95 4,95 9,95 14,95 V 2.4 Low or high level output voltage applies for worst case input conditions 2.4.1 B series Low or high level output voltage at |I 0 | 1 4A V IL= 1,5 V for V DD=5 V V IL= 3,0 V for V DD= 10 V V
29、 IL= 4,0 V for V DD= 15 V V OLA 5 10 15 0,5 1,0 1,5 0,5 1,0 1,5 0,5 1,0 1,5 V V IH= 3,5 V for V DD=5 V V IH= 7,0 V for V DD= 10 V V IH= 11,0 V for V DD= 15 V V OHB 5 10 15 4,5 9,0 13,5 4,5 9,0 13,5 4,5 9,0 13,5 V 2.4.2 UB series Low or high level output voltage at |I 0 | 1 4A V IL= 1,0 V for V DD=5
30、V V IL= 2,0 V for V DD= 10 V V IL= 2,5 V for V DD= 15 V V OLA 5 10 15 0,5 1,0 1,5 0,5 1,0 1,5 0,5 1,0 1,5 V V IH= 4,0 V for V DD=5 V V IH= 8,0 V for V DD= 10 V V IH= 12,5 V for V DD= 15 V V OHB 5 10 15 4,5 9,0 13,5 4,5 9,0 13,5 4,5 9,0 13,5 VBS CECC90104:1981 4 BSI 03-2000 NOTE 2Unless otherwise spe
31、cified in the detail specification. NOTE 3For devices with symmetrical outputs the values for I OHBare equal to those for I OLB . Symbol V DD (V) T amb= T amb min.T amb= + 25 C T amb= T amb max.Unit 2.5 Output low (sink) current (see Note 2) V IL= 0V, V IH= V DD 2.5.1 For full temperature range V 0=
32、 0,4 V V 0= 0,5 V V 0= 1,5 V 5 10 15 0,64 1,6 4,2 0,51 1,3 3,4 0,36 0,9 2,4 mA 2.5.2 For limited temperature range I OLB V 0= 0,4 V V 0= 0,5 V V 0= 1,5 V 5 10 15 0,52 1,3 3,6 0,44 1,1 3,0 0,36 0,9 2,4 2.6 Output high (source) current (see Note 2 and Note 3) V IL= 0 V, V IH= V DD 2.6.1 For full tempe
33、rature range V 0= 4,6 V V 0= 9,5 V V 0= 13,5 V I OHB 5 10 15 0,25 0,62 1,8 0,2 0,5 1,5 0,14 0,35 1,1 mA 2.6.2 For limited temperature range V 0= 4,6 V V 0= 9,5 V V 0= 13,5 V 5 10 15 0,2 0,5 1,4 0,16 0,4 1,2 0,12 0,3 1,0 2.7 Input leakage current V IL= 0 V, V IH= V DD |I IA | 4A 2.7.1 For full temper
34、ature range 15 0,1 0,1 1,0 2.7.2 For limited temperature range 15 0,3 0,3 1,0BS CECC90104:1981 BSI 03-2000 5 Symbol V DD (V) T amb= T amb min.T amb= + 25 C T amb= T amb max.Unit 2.8 Three-state output leakage current V IL= 0 V, V IH= V DDcombined to obtain a high impedance output state |I OZA | 4A 2
35、.8.1 For full temperature range 15 0,4 0,4 12 2.8.2 For limited temperature range 15 1,6 1,6 12 2.9 Input capacitance per unit load (any input) C IA 7,5 pF 2.10 Noise margin at low level output (equal to difference between V ILand V OLvalues as given in2.4) 2.10.1 B series V NLB 5 10 15 1 2 2,5 1 2
36、2,5 1 2 2,5 V 2.10.2 UB series 5 10 15 0,5 1 1 0,5 1 1 0,5 1 1 2.11 Noise margin at high level output (equal to difference between V IHand V OHvalues as given in2.4) 2.11.1 B series V NHB 5 10 15 1 2 2,5 1 2 2,5 1 2 2,5 V 2.11.2 UB series 5 10 15 0,5 1 1 0,5 1 1 0,5 1 1 2.12 Supply voltage range (to
37、 be tested at V DD= 5; 10 and15 V) V DDB +3 +3 +3 V V DDA + 15 + 15 + 15BS CECC90104:1981 6 BSI 03-2000 2.14 Supplementary information 2.14.1 Unused inputs: Unused inputs shall be connected to the appropriate logic voltage (e.g, either V SSor V DDor associated input). 2.14.2 Transient energy protect
38、ion C.MOS circuits have built-in protection circuits on all inputs to reduce the possibility of damage to the input gate oxide of the device by the transfer of electrostatic charge. Output gates may be similarly protected. A schematic may be given, for example: Generally used values: (see also relev
39、ant detail specification) R IS= 200 to 2 000 7 nom R OS= 10 to 1 000 7 nom Symbol V DD (V) T amb= T amb= T amb= T amb min.+ 25 C T amb max.Unit 2.13 Propagation and transition times t PLHA t PHLA Load networks: t TLHA For normal outputs: t THLA 5 t PHZA t PZHA 10 See relevant detail ns t TLZA specif
40、ication t TZLA 15 t PLZA For three-state outputs: t PZLA t THZA t TZHA BS CECC90104:1981 BSI 03-2000 7 BV D1= 50 to (80) to 120 V BV D2= 20 to 50 V BV D3= 20 to 50 V BV D4= 20 to 50 V BV D5= 20 to 50 V BV D6= 50 to (80) to 120 V BV D7= 20 to 50 V 2.14.3 Variation of parameters with temperature shoul
41、d be given in the format shown below; the curves given here show the general trend.BS CECC90104:1981 8 BSI 03-2000 2.14.4 Variation of switching times with load capacitance shall be given in the detail specification. Due to the very low input current requirements for C.MOS, there is practically no D
42、C output loading capability limitation when driving other C.MOS inputs. The actual fan-out of the C.MOS device is limited by a capacitance load consideration based on the desired system operating frequency. The effects of capacitive load on the dynamic characteristics shall be given. The curves show
43、n below give the general trend of transition times versus load capacitance, which implies the general trend of propagation times versus load capacitance. Normalized to C L= 50 pF value 3 Inspection requirements All tests shall be performed at T amb= 25 5 C unless otherwise stated. The clause numbers
44、 refer to the generic specification CECC90000, unless otherwise stated. The following abbreviations are used: All voltages referenced to the V SSterminal. IL = Inspection level AQL = Acceptable Quality Level n = Sample size c = Acceptance number P = Periodicity in months D = destructive ND = non des
45、tructive n.a. = not applicableBS CECC90104:1981 BSI 03-2000 9 Examination or test CECC 90000, clause No. D or ND Test conditions Assessment level Inspection requirements IL AQL Limits Group A: These tests are contained in the detail specification for the individual device type. They comprise the fol
46、lowing subgroups: Sub-group A1 Visual examination4.2 ND See relevant detail specification R, S, T, V I 1,5 See relevant detail specification Sub-group A2 Verification of the function ND See relevant detail specification R, S T, V II II 0,15 0,25 See relevant detail specification Sub-group A3 Static
47、characteristics at + 25 C ND See relevant detail specification R, S, T, V II 0,65 See relevant detail specification Sub-group A4 a Static characteristics at max. operatingtemperature ND See relevant detail specification R S T, V S-4 S-4 n.a. 10 2,5 n.a. See relevant detail specification Sub-group A4
48、 b Static characteristics at min operatingtemperature ND See relevant detail specification R S T,V S-4 S-4 n.a. 1,0 2,5 n.a. See relevant detail specification Sub-group A5 Dynamic characteristics at+25 C ND See relevant detail specification R S, T, V S-4 S-4 1,5 2,5 See relevant detail specification
49、 Group B: Sub-group B1 Dimensions 4.3 ND IEC outline (see IEC Publication191-2 and see detail specification for specific type) R, S, T, V S-4 1,0 See relevant detail specification Sub-group B2 Solderability 4.6.10.1 D Solder bath method No ageing required R, S, T, V S-3 2,5 4.6.10.1 Sub-group B3 Sealing tests (cavity packages) ND R, S, T, V II 1,0 Fine leak 4.6.9.1 Gross leak 4.6.9.2 4.6.9.1 test Qk 4.6.9.2 test Qc 4.6.9.1 4.6.9.2BS CECC90104:1981 10 BSI 03-2000 Examination or t
