1、BSI Standards PublicationBS EN 16602-60-12:2014Space product assurance Design, selection, procurementand use of die form monolithicmicrowave integrated circuits(MMICs)BS EN 16602-60-12:2014 BRITISH STANDARDNational forewordThis British Standard is the UK implementation ofEN 16602-60-12:2014.The UK p
2、articipation in its preparation was entrusted to Technical Committee ACE/68, Space systems and operations.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract. Users a
3、re responsible for its correct application. The British Standards Institution 2014.Published by BSI Standards Limited 2014ISBN 978 0 580 84416 4 ICS 49.140 Compliance with a British Standard cannot confer immunity from legal obligations.This British Standard was published under the authority of the
4、Standards Policy and Strategy Committee on 30 September 2014.Amendments/corrigenda issued since publicationDate T e x t a f f e c t e dEUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN 16602-60-12 September 2014 ICS 49.140 English version Space product assurance - Design, selection, procurement a
5、nd use of die form monolithic microwave integrated circuits (MMICs) Assurance produit des projets spatiaux - Conception, slection, approvisionnement et utilisation de circuits intgrs monolithique hyperfrquence de forme die Raumfahrtproduktsicherung - Design, Auswahl, Beschaffung und Nutzung von MMIC
6、 This European Standard was approved by CEN on 13 March 2014. CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliogr
7、aphical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under th
8、e responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions. CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia
9、, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and Unit
10、ed Kingdom. CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels 2014 CEN/CENELEC All rights of exploitation in any form and by any means reserved worldwide for CEN national Members and for CENELEC Members. Ref. No. EN 16602-60-12:2014 EBS EN 16602-60-12:2014Table of contents Foreword 6
11、Introduction 7 1 Scope . 8 2 Normative references . 9 3 Terms, definitions and abbreviated terms 10 3.1 Terms from other standards 10 3.2 Terms specific to the present document . 10 3.3 Abbreviated terms. 12 4 General requirements. 14 4.1 Overview 14 4.2 Flight model MMIC dies lots procurement . 14
12、4.3 Minimum quality requirements 14 5 Selection 15 5.1 General . 15 5.1.1 Overview . 15 5.1.2 Requirements 15 5.2 Process selection 16 5.3 Models, and design tools 16 6 Responsibilities 17 7 MMIC design . 18 7.1 Principles of MMIC design 18 7.1.1 Overview . 18 7.1.2 General . 18 7.1.3 Number of desi
13、gn iterations 18 7.1.4 Design trade-offs . 19 7.2 Design tasks . 19 7.2.1 Electrical design specification . 19 7.2.2 Design variations 19 EN 16602-60-12:2014 (E)BS EN 16602-60-12:20147.2.3 Parasitic effects . 19 7.2.4 Transient simulation 20 7.2.5 Thermal analysis . 20 7.2.6 Sensitivity to temperatu
14、re, process variation and supply voltages . 20 7.2.7 Design testability . 21 7.2.8 Design stability analysis 21 7.2.9 Maximum rating and robustness . 21 7.2.10 Layout optimization . 22 7.2.11 DRC or ERC . 22 7.3 Design reviews . 23 7.3.1 General . 23 7.3.2 MMIC architecture . 23 7.3.3 Schematic . 23
15、 7.3.4 Simulation results 23 7.3.5 Sensitivity and stability analysis 24 7.3.6 Derating 24 7.3.7 Layout . 24 7.3.8 Tests matrix 24 7.3.9 Assembly 24 7.3.10 Compliance matrix 25 7.3.11 MMIC detail specification 25 7.3.12 Development plan . 25 7.3.13 Design documentation 25 7.3.14 MMIC summary design
16、sheet 25 8 Application approval 26 8.1 General . 26 8.2 Test flow and test procedures . 26 9 Procurement and LAT specification . 28 10 Procurement . 29 10.1 General . 29 10.1.1 Overview . 29 10.1.2 Methodology . 29 10.2 Wafer screening and WAT 29 10.2.1 General . 29 10.2.2 Wafer screening and WAT fl
17、ows . 29 10.2.3 Wafer manufacturing and control 30 EN 16602-60-12:2014 (E)BS EN 16602-60-12:201410.2.4 Wafer acceptance test 31 10.2.5 Packaging . 32 10.2.6 Deliverables 32 10.3 Dies incoming testing 33 10.3.1 General . 33 10.3.2 Assembly test 33 10.3.3 Visual inspection . 34 10.3.4 Electrical chara
18、cterization . 34 10.4 User LAT procurement sequences . 35 10.4.1 General . 35 10.4.2 Sequence A: process, design and application validated 38 10.4.3 Sequence B: process validated and new design or new application 38 10.4.4 Sequence C: process, design and application not validated 39 10.4.5 Sequence
19、D: application approval testing . 40 10.4.6 Destructive physical analysis after user LAT . 40 10.5 Failure criteria and lot failure . 41 Annex A (normative) MMIC electrical design specification - DRD 42 Annex B (normative) Compliance matrix for custom MMIC design - DRD . 43 Annex C (normative) Desig
20、n package document - DRD 44 Annex D (normative) MMIC summary design sheet - DRD 46 Annex E (normative) MMIC procurement specification - DRD . 47 Annex F (normative) MMIC lot acceptance specification for user LAT - DRD 48 Annex G (normative) MMIC visual inspection summary sheet - DRD . 50 Annex H (in
21、formative) References . 51 Bibliography . 52 Figures Figure 10-1: Wafer screening and WAT . 30 Figure 10-2: Dies or die incoming testing . 34 Figure 10-3: Acceptance flow for flight model die lots . 35 Figure 10-4: User LAT flow . 37 EN 16602-60-12:2014 (E)BS EN 16602-60-12:2014Tables Table 6-1: Cus
22、tomer and supplier responsibilities for the “foundry” and “catalogue” modes 17 Table 8-1: CTA tests and procedures for testing in sequence D . 27 EN 16602-60-12:2014 (E)BS EN 16602-60-12:2014Foreword This document (EN 16602-60-12:2014) has been prepared by Technical Committee CEN/CLC/TC 5 “Space”, t
23、he secretariat of which is held by DIN. This standard (EN 16602-60-12:2014) originates from ECSS-Q-ST-60-12C. This European Standard shall be given the status of a national standard, either by publication of an identical text or by endorsement, at the latest by March 2015, and conflicting national s
24、tandards shall be withdrawn at the latest by March 2015. Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CEN and/or CENELEC shall not be held responsible for identifying any or all such patent rights. This document has been prepar
25、ed under a mandate given to CEN by the European Commission and the European Free Trade Association. This document has been developed to cover specifically space systems and has therefore precedence over any EN covering the same scope but with a wider domain of applicability (e.g. : aerospace). Accor
26、ding to the CEN-CENELEC Internal Regulations, the national standards organizations of the following countries are bound to implement this European Standard: Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany,
27、 Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom. EN 16602-60-12:2014 (E)BS EN 16602-60-12:2014Introduction This Standard covers the design, s
28、election, procurement and use of III-V monolithic microwave integrated circuits (MMICs) for space equipment. It defines the design activity for the technical (methodology, phases to be followed) and quality (quality assurance, design review) aspects, and, the selection and procurement rules for thes
29、e components taking into account whether or not the processes have been validated. EN 16602-60-12:2014 (E)BS EN 16602-60-12:20141 Scope This Standard applies to all types of MMIC (monolithic microwave integrated circuit) based on III-V compound materials for RF applications (i.e. frequency range 1 G
30、Hz). The requirements for the procurement of components in die form are defined. It is not within the scope of this Standard to address packaged MMICs and discrete microwave components, these are dealt with in the relevant ESCC specification (ESCC 9010 and ESCC 5010). This standard may be tailored f
31、or the specific characteristic and constraints of a space project in conformance with ECSS-S-ST-00. EN 16602-60-12:2014 (E)BS EN 16602-60-12:20142 Normative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this ECSS Stand
32、ard. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this ECSS Standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For
33、undated references the latest edition of the publication referred to applies. EN reference Reference in text Title EN 16601-00-01 ECSS-S-ST-00-01 ECSS system Glossary of terms EN 16602-30-11 ECSS-Q-ST-30-11 Space product assurance Derating - EEE components EN 16602-60 ECSS-Q-ST-60 Space product assu
34、rance - Electrical, electronic and electromechanical (EEE) components EN 16602-60-05 ECSS-Q-ST-60-05 Space product assurance Generic requirements for hybrids MIL-STD-883 Tests methods and procedures for microelectronics ESCC 20600 Preservation, packaging and despatch of ESCC electronic components ES
35、CC 24600 Minimum quality management system requirements ESCC 2049010 Internal visual inspection of monolithic microwave devices ESCC 2439010 Requirements for capability approval of MMICs ESCC 9010 Generic specification for MMICs EN 16602-60-12:2014 (E)BS EN 16602-60-12:20143 Terms, definitions and a
36、bbreviated terms 3.1 Terms from other standards For the purpose of this document, the terms and definitions given in ECSS-S-ST-00-01 apply. For the purpose of this document, the following term from ECSS-Q-ST-60-05 applies: process identification document 3.2 Terms specific to the present document 3.
37、2.1 batch lot wafers from the same basic raw materials processed as a single set in the manufacturing sequence (diffusion, metallization and passivation process) in a limited and controlled period of time NOTE A unique identifier or code is assigned to a batch lot and to each wafer for processing tr
38、aceability purposes. 3.2.2 design rules check control procedure for verifying that design rules have been satisfied NOTE 1 Design rules checks are generally issued by the supplier. NOTE 2 DRC is performed using software. 3.2.3 designer organization responsible for the design of the MMICs 3.2.4 die l
39、ot set of all dies coming from a single wafer lot 3.2.5 electrical rule check control procedure for verifying that the electrical rules have been satisfied NOTE Electrical rules are generally issued by the manufacturer. EN 16602-60-12:2014 (E)BS EN 16602-60-12:20143.2.6 evaluated process mature tech
40、nology that has been successfully submitted to a set of electrical and environmental testing to demonstrate performance and reliability limits NOTE 1 ECSS-Q-ST-60-01 contains a list of evaluated processes. NOTE 2 The ESCC 2269010 specification defines the requirements for the evaluation. 3.2.7 manuf
41、acturer foundry responsible for the manufacturing of the MMICs 3.2.8 process control monitor test vehicle used by the supplier to assess the stability of the manufacturing process by means of controls conducted during a wafer production cycle NOTE The PCM is repeated a number of times (depending on
42、the manufacturers) on each wafer lot. The measurements taken during the PCM are used to accept or reject the wafer according to the relevant DC and RF criteria defined in the design manual. 3.2.9 production lot device types manufactured from the same basic raw materials on the same production line,
43、processed under the same manufacturing techniques and controls using the same type of equipment NOTE A production lot may be composed of one or many batch lots. 3.2.10 qualified process process that has been successfully submitted to a formal qualification testing NOTE The ESCC 20100 specification d
44、efines the requirements for the qualification. 3.2.11 reticule group of circuit layouts (MMIC, TCV, DEC, PCM) defined by design at the mask level, for duplication over the entire wafer during the MMIC manufacturing 3.2.12 statistical process control tool to control the quality and the stability of t
45、he technological process NOTE SPC is implemented by measuring key parameters during the different manufacturing steps and their analysis using appropriate methods. 3.2.13 tile See reticule EN 16602-60-12:2014 (E)BS EN 16602-60-12:20143.2.14 user entity responsible for the integration of the MMICs at
46、 upper level NOTE Example: MMICs are integrated by users into, for example, modules, hybrids, piece of equipment. 3.2.15 validated design design that is successfully submitted to application approval testing and an MMIC user LAT test 3.2.16 validated process process that is evaluated or qualified 3.
47、2.17 wafer lot wafers manufactured from one or more batch lots NOTE Depending on the maturity of the process a wafer lot is defined as follows: Case 1 (non-evaluated or qualified process): a wafer lot is a single wafer. Case 2 (evaluated or qualified process and new MMIC design): a wafer lot is one
48、batch lot. Case 3 (mature process and recurrent MMIC design): a wafer lot is considered to be a production lot of 4 batches manufactured within a 3 month period. 3.3 Abbreviated terms For the purpose of this standard, the abbreviated terms of ECSS-S-ST-00-01 and the following apply: Abbreviation Mea
49、ning AQL acceptance quality level CTA circuit type approval DEC dynamic evaluation circuit DRC design rules check ERC electrical rule check HTRB high-temperature reverse bias LAT lot acceptance test LTRB low-temperature reverse bias MMIC monolithic microwave integrated circuit PAD part approval document PCM process control monitor PID process identification document EN 16602-60-12:2014 (E)BS EN 16602-60-12:2014RGA residual gas analysis SAM scanning acoustic microscopy SEM scanning electron microscope SEU single event upset SPC statistical process control TCV technolog
