1、BRITISH STANDARD BS CECC 90109:1986 Specification for Harmonized system of quality assessment forelectronic components Familyspecification Digital integrated HC MOS circuits series HC/HCT/HCUBSCECC90109:1986 BSI05-2000 ISBN 0 580 34637 4 Amendments issued since publication Amd. No. Date CommentsBSCE
2、CC90109:1986 BSI 05-2000 i Contents Page National foreword ii Foreword iii 1 Limiting conditions of use for the family 1 2 Recommended operating conditions and associated characteristics for the family 2 3 Inspection requirements 12BSCECC90109:1986 ii BSI 05-2000 National foreword This BritishStanda
3、rd has been prepared under the direction of the Electronic Components Standards Committee. It is identical with CENELEC Electronic Components Committee (CECC)90109:1986 “Family specification: Digital integrated HC MOS circuits series HC/HCT/HCU”. This standard is a harmonized specification within th
4、e CECC System. Terminology and conventions. The text of the CECC specification has been approved as suitable for publication as a BritishStandard without deviation. Some terminology and certain conventions are not identical with those used in BritishStandards; attention is drawn especially to the fo
5、llowing. The comma has been used as a decimal marker. In BritishStandards it is current practice to use a full point on the baseline as the decimal marker. Cross-references. The BritishStandard which implements CECC00100 is BS9000: “General requirements for a system for electronic components of asse
6、ssed quality”. Part2:1983 “Specification for national implementation of CECC basic rules and rules of procedure”. The Technical Committee has reviewed the provisions of IEC747, to which reference is made in the text, and has decided that they are acceptable for use in conjunction with this standard.
7、 Scope. This standard lists the ratings, characteristics and inspection requirements which shall be included as mandatory requirements in accordance with BS CECC90100 in any detail specification for these devices. Detail specification layout. The front page layout of detail specifications released t
8、o BS CECC family or blank detail specifications will be in accordance with BS9000 Circular letter No.15. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Stan
9、dard does not of itself confer immunity from legal obligations. International Standards a Corresponding BritishStandards CECC90000:1985 BS CECC90000:1985 Harmonized system of quality assessment for electronic components. Generic specification: monolithic integrated circuits (Identical) CECC90100:198
10、6 BS CECC90100:1986 Harmonized system of quality assessment for electronic components. Sectional specification: digital monolithic integrated circuits (Identical) a Undated in text. Summary of pages This document comprises a front cover, an inside front cover, pagesi andii, theCECC title page, pages
11、 ii to iv, pages1 to23 and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover.CECC90109:1986 ii BSI 05-2000 Foreword The CENELEC Electronic Components Committee (CECC) is
12、composed of those member countries of the European Committee for Electrotechnical standardization (CENELEC) who wish to take part in harmonized System for electronic component of assessed quality. The object of the System is to facilitate international trade by the harmonization of the specification
13、s and quality assessment procedures for electronic components, and by the grant of an internationally recognized Mark, or Certificate, of Conformity. The components produced under the System are thereby accepted by all member countries without further testing. This specification has been formally ap
14、proved by the CECC, and has been prepared for those countries taking part in the system who wish to issue national harmonized specifications for HC MOS DIGITAL INTEGRATED CIRCUITS. It should be read in conjunction with the current regulations for the CECC system. At the date of printing of this spec
15、ification the member countries of the CECC areAustria, Belgium, Denmark, Finland, France, Germany, Ireland, Italy, theNetherlands, Norway, Portugal, Spain, Sweden, Switzerland, and theUnitedKingdom. Preface This family specification was prepared by CECC WG9 “Integrated circuits”. It is based, wherev
16、er possible, on the Publications of the International Electrotechnical Commission and in particular on IEC747: Semiconductor devices Discrete devices and integrated circuits. It contains general information on HC MOS digital integrated circuits and defines the common characteristics for this family
17、of integrated circuits. Together with the device type detail specification (DS) of a component usually prepared nationally, this family specification forms a complete detail specification. The text of this specification was circulated to the CECC for voting in the documents indicated below and was r
18、atified by the President of the CECC for printing as a CECC specification. In accordance with the decision of the CECC Management Committee this specification is published initially in English and French. The German text will follow as soon as it has been prepared. Document Date of voting Report on
19、the voting CECC (Secretariat)1608 March1985 CECC (Secretariat)1725CECC90109:1986 BSI 05-2000 iiiiv blankCECC90109:1986 BSI 05-2000 1 1 Limiting conditions of use for the family (Not for inspection purposes) 1.1 Maximum supply voltage positive V CC =+7V 1.2 Maximum supply voltage negative V CC =0,5V
20、1.3.1 Maximum DC input protection diode current I IK = 20mA V I V CC OR (whichever is the worst case) 1.3.2 Maximum input voltage V I =V CC +0,5V 1) V I =0,5V 1) NOTEExcept for transient energy (see2.14.2) 1.4.1 Maximum DC output diode current I OK = 20mA V O V CC OR (whichever is the worst case) 1.
21、4.2 Maximum output voltage V O =V CC +0,5V 1) V O =0,5V 1) 1.5 Maximum DC, output source or sink current per output pin I O 25mA (standard outputs) 1) 35mA (bus driver outputs) 1) 1.6 Maximum DC, V CCor Ground pin current I CCor I GND 50mA (standard outputs) 1) 70mA (bus driver outputs) 1) 1.7 Ambie
22、nt operating temperature range T amb 74HC: 40 C to+85 C 54HC:55 C to+125 C 1.8 Storage temperature range T stg 65 C to+150 C 1) Unless otherwise specified in detail specification.CECC90109:1986 2 BSI 05-2000 2 Recommended operating conditions and associated characteristics for thefamily (Note for in
23、spection purposes) These conditions apply over the operating temperature range, unless otherwise specified in the DS. All voltages are referenced to ground. HC SERIES: Operating supply voltages V CCB =2V to V CCA =6V Parameters Symbol V CC(V) T amb Unit 54/74HC (1) 74HC (2) 54HC (3) min. max. min. m
24、ax. min. max. 2.1 Quiescent supply current V I =0or V CC I O =0 S.S.I. FF (Bistable) MSI I CCA 6 6 6 2 4 8 20 40 80 40 80 160 A A A 2.2 High level input voltage V IHB 2 4,5 6 1,5 3,15 4,2 1,5 3,15 4,2 1,5 3,15 4,2 V V V 2.3 Low level input voltage V ILA 2 4,5 6 0,3 0,9 1,2 0,3 0,9 1,2 0,3 0,9 1,2 V
25、V V 2.4 High level output voltage V I =V IHBor V ILA 2.4.1 I O =20A 2.4.2 I O =4mA (standard outputs) I O =6mA (bus driver outputs) I O =5,2mA (standard outputs) I O =7,8mA (bus driver outputs) V OHB 2 4,5 6 4,5 6 1,9 4,4 5,9 3,98 5,48 1,9 4,4 5,9 3,84 5,34 1,9 4,4 5,9 3,7 5,2 V V V V V 2.5 Low leve
26、l output voltage V I =V IHBor V ILA 2.5.1 I O =+20A 2.5.2 I O = +4mA (standard outputs) I O =+ 6mA (bus driver outputs) I O =+ 5,2mA (standard outputs) I O =+ 7,8mA (bus driver outputs) V OLA 2 4,5 6 4,5 6 0,1 0,1 0,1 0,26 0,26 0,1 0,1 0,1 0,33 0,33 0,1 0,1 0,1 0,4 0,4 V V V V V 2.6 Input leakage cu
27、rrent V I =0 or V CC I| IA | 6 0,1 1 1 A (1)25 C (2)40 C to+85 C (3)55 C to+125 C CECC90109:1986 BSI 05-2000 3 HCT SERIES: Operating supply voltages V CCB =4,5V to V CCA =5,5V Parameters Symbol V CC(V) T amb Unit 54/74HC (1) 74HC (2) 54HC (3) min. max. min. max. min. max. 2.7 Analogue switch off-sta
28、te current per channel V I =V IHBor V ILA |V S |=V CCor V CC V EE (4) |I SA | 6 0,1 1 1 A 2.8 3 state output off-state current V I =V IHBor V ILA V O =0 or V CC 2.9 Capacitance 2.9.1 Input capacitance(5) 2.9.2 Output capacitance 3state outputs(6) |I OZA | C IA C OZ 6 4,5 0,5 10 5 10 10 10 A pF 2.10
29、Noise margin at low level output (V ILA V OLA ) I O =+20A V NLB 2 4,5 6 0,2 0,8 1,1 0,2 0,8 1,1 0,1 0,8 1,1 V V V 2.11 Noise margin at high level output (V OHB V IHB ) I O =20A V NHB 2 4,5 6 0,4 1,25 1,7 0,4 1,25 1,7 0,4 1,25 1,7 V V V 2.12 Input rise and fall time (except for Schmitt inputs) t r ,
30、t f 2 4,5 6 0 0 0 1000 500 400 0 0 0 1000 500 400 0 0 0 1000 500 400 ns ns ns (1)25 C (2) 40 C to+85 C (3) 55 C to+125 C (4) V EE : additional negative supply voltage for some analogue switches, to be specified in the DS. (5) Unless otherwise specified in the DS. (6) If specified in the DS. Paramete
31、rs Symbol V CC(V) T amb Unit 54/74HC (1) 74HC (2) 54HC (3) min. max. min. max. min. max. 2.1 Quiescent supply current 2.1.1 V I =0 or V CC I O =0 S.S.I. FF (Bistable) MSI I CCA 5,5 5,5 5,5 2 4 8 20 40 80 40 80 160 A A A 2.2 High level input voltage V IHB 5,5 2 2 2 V 2.3 Low level input voltage V ILA
32、 4,5 0,8 0,8 V (1)25 C (2) 40 C to + 85 C (3)55 C to+125 CCECC90109:1986 4 BSI 05-2000 Parameters Symbol V CC(V) T amb Unit 54/74HC (1) 74HC (2) 54HC (3) min. max. min. max. min. max. 2.4 High level output voltage V I =V IHBor V ILA 2.4.1 I O =20A 2.4.2 I O =4mA (standard outputs) I O =6mA (bus driv
33、er outputs) V OHB 4,5 4,5 4,4 3,98 4,4 3,84 4,4 3,7 V V 2.5 Low level output voltage V I =V IHBor V ILA 2.5.1 I O =+20A 2.5.2 I O =+4mA (standard outputs) I O =+6mA (bus driver outputs) V OLA 4,5 4,5 0,1 0,26 0,1 0,33 0,1 0,4 V V 2.6 Input leakage current 2.6.1 V I =0 or V CC 2.6.2 V I =V IHB |I IA
34、| 5,5 5,5 0,1 100 1 125 1 150 A A 2.7 Analogue switch off-state current per channel V I =V IHBor V ILA |V S |=V CCor V CC V EE (4) |I SA | 5,5 0,1 1 1 A 2.8.3 state output off-state current V I =V IHBor V ILA V O =0 or V CC |I OZA | 5,5 0,5 5 10 A 2.9 Capacitance 2.9.1 Input capacitance(5) 2.9.2 Out
35、put capacitance 3state outputs(6) C IA C OZ 5 10 10 10 pF 2.10 Noise margin at low level output (V ILA V OLA ) I O =+4mA (standard outputs) I O =+6mA (bus driver outputs) V NLB 4,5 0,54 0,47 0,4 V 2.11 Noise margin at high level output (V OHB V IHB ) I O =+4mA (standard outputs) I O =+6mA (bus drive
36、r outputs) V NHB 4,5 1,98 1,84 1,7 V 2.12 Input rise and fall time (except for Schmitt inputs) t r , t f 4,5 0 500 0 500 0 500 ns (1)25 C (2) 40 C to + 85 C (3)55 C to+125 C (4) V EE : additional negative supply voltage for some analogue switches, to be specified in the DS. (5) Unless otherwise spec
37、ified in the DS. (6) If specified in the DS. CECC90109:1986 BSI 05-2000 5 HCU SERIES: Operating supply voltages V CCB =2V to V CCA =6V Parameters Symbol V CC(V) T amb Unit 54/74HC (1) 74HC (2) 54HC (3) min. max. min. max. min. max. 2.1 Quiescent supply current V I =0 or V CC I O =0 S.S.I. FF (Bistab
38、le) MSI I CCA 6 6 6 2 4 8 20 40 80 40 80 160 A A A 2.2 High level input voltage V IHB 2 4,5 6 1,7 3,6 4,8 1,7 3,6 4,8 1,7 3,6 4,8 V V V 2.3 Low level input voltage V ILA 2 4,5 6 0,3 0,8 1,1 0,3 0,8 1,1 0,3 0,8 1,1 V V V 2.4 High level output voltage 2.4.1 V I =V IHBor V ILA I O =20A 2.4.2 V I =0or V
39、 CC I O =4mA I O =5,2mA V OHB 2 4,5 6 4,5 6 1,8 4 5,5 3,98 5,48 1,8 4 5,5 3,84 5,34 1,8 4 5,5 3,7 5,2 V V V V V 2.5 Low level output voltage 2.5.1 V I =V IHBor V ILA I O =+20A 2.5.2 V I =0or V CC I O =+4mA I O =+5,2mA V OLA 2 4,5 6 4,5 6 0,2 0,5 0,5 0,26 0,26 0,2 0,5 0,5 0,33 0,33 0,2 0,5 0,5 0,4 0,
40、4 V V V V V 2.6 Input leakage current V I =0 or V CC |I IA | 6 0,1 1 1 A 2.7 (not applicable) 2.8 (not applicable) 2.9 Capacitance 2.9.1 Input capacitance (5) 2.9.2 (not applicable) C IA 4,5 15 15 15 pF 2.10 Noise margin at low level output (V ILA V OLA ) I O =+20A V NLB 2 4,5 6 0,1 0,3 0,6 0,1 0,3
41、0,6 0,1 0,3 0,6 V V V 2.11 Noise margin at high level output (V OHB V IHB ) I O =20A V NHB 2 4,5 6 0,1 0,4 0,7 0,1 0,4 0,7 0,1 0,4 0,7 V V V 2.12 (not applicable) (1)25 C (2)40 C to+85 C (3)55 C to+125 C (5) Unless otherwise specified in the DS.CECC90109:1986 6 BSI 05-2000 2.13 Dynamic characteristi
42、cs (Series HC, HCT, HCU) 2.13.1 Pulse generator and driving circuit The following conditions shall be met: Output impedance of pulse generator:507 10% Impedance of the driving circuit cable from the generator, including the test equipment:507 10% Low level input voltage:0V 0,1 V High level input vol
43、tage: V CC 0,1V (Series HC, HCU);3V 0,1V (Series HCT) Rise time of the input signal: t r =6ns 1ns (measured from10% to90% of the stop amplitude) Fall time of the input signal: t f =6ns1ns (measured from90% to10% of the stop amplitude) Pulse repetition frequency: u 1 MHz 2.13.2 Output transition time
44、 specifications (HC, HCT) Parameters Symbol V CC(V) T amb Unit 54/74HC/HCT (1) 74HC/HCT (2) 54HC/HCT (3) Standard output types Bus driver output types t THLand t TLH 2 4,5 a 6 2 4,5 a 6 75 15 13 60 12 10 95 19 16 75 15 13 110 22 19 90 18 15 ns ns ns ns ns ns (1)25 C (2) 40 C to+85 C (3) 55 C to+125
45、C a 54/74HCT specificationCECC90109:1986 BSI 05-2000 7 2.13.3 Switching waveforms and loading circuits 1) Switching waveforms for54/74HC and54/74HCU Output should be switching from10% V CCto90% V CCin accordance with device truth table. For t maxinput duty cycle=50% Transition times and propagation
46、delay times Clock-pulse rise and fall times and pulse widthCECC90109:1986 8 BSI 05-2000 Set up times, hold times, removal time and propagation delay times for edge triggered sequential logic circuits Recovery time: Clock recovery time. This is the time that an active clear or enable signal must be r
47、emoved before the clock input transitions. Three-state outputs (54/74 HC only) Open drain and channel waveforms t PLZ , t PZLwaveforms same as3-state Loading circuit Three-state propagation delay wave shapes Loading circuitCECC90109:1986 BSI 05-2000 9 2) Switching waveforms for54/74HCT Outputs shoul
48、d be switching from10% V CCto90% V CCin accordance with device truth table. For t maxinput duty cycle=50% Transition times and propagation delay times Clock-pulse rise and fall times and pulse widthCECC90109:1986 10 BSI 05-2000 Set up times, hold times, removal time and propagation delay times for e
49、dge triggered sequential logic circuits Recovery time: Clock recovery time. This is the time that an active clear or enable signal must be removed before the clock input transitions. Three-state outputs t PLZ , t PZLwaveforms same as3-state 2.13.4 Dynamic characteristics value in accordance with DS. 2.14 Supplementary information 2.14.1 Unused inputs Unused inputs shall be connected to
