1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationMechanical standardization of semiconductor devicesPart 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide
2、for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)BS EN 60191-6-22:2013National forewordThis British Standard is the UK implementation of EN 60191-6-22:2013. It isidentical to IEC 60191-6-22:2012.The UK participation in its prepar
3、ation was entrusted to Technical CommitteeEPL/47, Semiconductors.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions of acontract. Users are responsible for its correct application.
4、 The British Standards Institution 2013Published by BSI Standards Limited 2013ISBN 978 0 580 75720 4ICS 31.080.01Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of the StandardsPolicy and Strategy Committee on 30
5、 April 2013.Amendments issued since publicationAmd. No. Date Text affectedBRITISH STANDARDBS EN 60191-6-22:2013EUROPEAN STANDARD EN 60191-6-22 NORME EUROPENNE EUROPISCHE NORM March 2013 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Eu
6、ropisches Komitee fr Elektrotechnische Normung Management Centre: Avenue Marnix 17, B - 1000 Brussels 2013 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 60191-6-22:2013 E ICS 31.080.01 English version Mechanical standardization
7、of semiconductor devices - Part 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA) (IEC 60191-6-22:2012) N
8、ormalisation mcanique des dispositifs semiconducteurs - Partie 6-22: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs montage en surface - Guide de conception pour les botiers matriciels billes et pas fins en silicium et botiers matriciels zone de contact pl
9、ate et pas fins en silicium (S-FBGA et S-FLGA) (CEI 60191-6-22:2012) Mechanische Normung von Halbleiterbauelementen - Teil 6-22: Allgemeine Regeln fr die Erstellung von Gehusezeichnungen von SMD-Halbleitergehusen - Konstruktionsleitfaden fr Halbleitergehuse Si-Feinraster-Ball-Grid-Array und Si-Feinr
10、aster-Land-Grid-Array (S-FBGA und S-FLGA) (IEC 60191-6-22:2012) This European Standard was approved by CENELEC on 2013-01-15. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standa
11、rd without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in
12、 any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croat
13、ia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turke
14、y and the United Kingdom. BS EN 60191-6-22:2013EN 60191-6-22:2013 - 2 - Foreword The text of document 47D/812/CDV, future edition 1 of IEC 60191-6-22, prepared by SC 47D, “Semiconductor packaging“, of IEC TC 47, “Semiconductor devices“ was submitted to the IEC-CENELEC parallel vote and approved by C
15、ENELEC as EN 60191-6-22:2013. The following dates are fixed: latest date by which the document has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2013-10-15 latest date by which the national standards conflicting with the document have to
16、 be withdrawn (dow) 2016-01-15 Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CENELEC and/or CEN shall not be held responsible for identifying any or all such patent rights. Endorsement notice The text of the International Standa
17、rd IEC 60191-6-22:2012 was approved by CENELEC as a European Standard without any modification. In the official version, for Bibliography, the following notes have to be added for the standards indicated: IEC 60191-6 NOTE Harmonized as EN 60191-6. IEC 60191-6-5 NOTE Harmonized as EN 60191-6-5. IEC 6
18、0191-6-12 NOTE Harmonized as EN 60191-6-12. BS EN 60191-6-22:2013 2 60191-6-22 IEC:2012 CONTENTS 1 Scope . 5 2 Normative references . 5 3 Terms and definitions . 5 4 Terminal position numbering . 5 5 Code of package nominal dimensions . 5 6 Symbols and drawings 6 7 Dimensions 9 7.1 Group 1 . 9 7.2 G
19、roup 2 . 11 8 Combination list of D, E, MD, and ME12 Bibliography 17 Figure 1 S-FBGA outline 6 Figure 2 S-FLGA outline 7 Figure 3 Mechanical gauge drawinge). 8 Figure 4 Array of terminal-existence areasf). 8 Table 1 Dimensions and tolerances in Group 1 9 Table 2 Dimensions and tolerances of Group 2
20、11 Table 3 e= 0,80 mm pitch S-FBGA and S-FLGA . 12 Table 4 e= 0,65 mm pitch S-FBGA and S-FLGA . 12 Table 5 e= 0,50 mm pitch S-FBGA and S-FLGA . 13 Table 6 e= 0,40 mm pitch S-FBGA and S-FLGA . 14 Table 7 e= 0,30 mm pitch S-FBGA and S-FLGA . 15 Table 8 e= 0,25 mm pitch S-FLGA . 16 BS EN 60191-6-22:201
21、360191-6-22 IEC:2012 5 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Arr
22、ay (S-FBGA and S-FLGA) 1 Scope This part of IEC 60191 provides the outline drawings and dimensions common to silicon-based package structures and materials of ball grid array packages (BGA) and land grid array packages (LGA). 2 Normative references The following documents, in whole or in part, are n
23、ormatively referenced in this document and are indispensable for its application. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. Void 3 Terms and definitions For the purpose of this docum
24、ent, the following terms and definitions apply. 3.1 S-FBGA FBGA composed of silicon die, dielectric layer(s) on the die, rerouting wires from the die pads to outer balls on the dielectric layer(s), and outer balls with heights more than 0,1 mm 3.2 S-FLGA FLGA composed of silicon die, dielectric laye
25、r(s) on the die, rerouting wires from the die pads to outer lands on the dielectric layer(s), and outer lands with heights of 0,1 mm or less 4 Terminal position numbering When a package is viewed from the terminal side with the index corner in the bottom left corner position, terminal rows are lette
26、red from bottom to top starting with A, then B, C, AA, AB, etc., whereas terminal columns are numbered from left to right starting with 1. Terminal positions are designated by a row-column grid system and shown as alphanumeric identification, e.g., A1, B1. The letters I, O, Q, S, X and Z shall not b
27、e used for naming the terminal rows. 5 Code of package nominal dimensions A code of package nominal dimensions is defined as the combination of package width E and length D which are shown in the second decimal place in millimeter. BS EN 60191-6-22:2013 6 60191-6-22 IEC:2012 6 Symbols and drawings S
28、ymbols and drawings are shown in Figures 1, 2, 3 and 4. a) B E Ay1S S A1Ae ey CZ (ZE) (ZD)n b d)Top view Side view Bottom view DD C B A 1 2 3 4 x1M A M B M c)S S x2M b) IEC 2310/12 Figure 1 S-FBGA outline BS EN 60191-6-22:201360191-6-22 IEC:2012 7 a) B E Ay1S S A1Ae ey CZ (ZE) (ZD)n b d)Top view Sid
29、e view Bottom view DD C B A 1 2 3 4 x1M A M B M c)S S x2M b) IEC 2311/12 Figure 2 S-FLGA outline BS EN 60191-6-22:2013 8 60191-6-22 IEC:2012 e ee eb3EmaxDmaxb4IEC 2312/12 IEC 2313/12 Figure 3 Mechanical gauge drawinge)Figure 4 Array of terminal-existence areasf)Footnotes relating to Figures 1 to 4 a
30、) Datum S is the seating plane on which a package stays. b) The hatched zone is an index-marking area indicating A1 corner. c) True positional tolerances of terminals, x1and x2, are applied to all terminals. d) The terminal diameter b is the maximum diameter of the ball as measured in a plane parall
31、el to the seating plane. e) An array of terminal-existence areas with regard to the datum S , A , and B is shown in the mechanical gauge drawing in Figure 3. f) The array of terminal-existence areas with regard to the datum S is shown in Figure 4. BS EN 60191-6-22:201360191-6-22 IEC:2012 9 7 Dimensi
32、ons 7.1 Group 1 Group 1 dimensions are shown in Table 1. Table 1 Dimensions and tolerances in Group 1 Dimensions in millimeters Term Symbol Specification Recommended value Notes Code of package nominal dimensions E D Code of package nominal dimension is defined as the combination of package width E
33、and length D, which are shown in the second decimal place in millimeter. Package length D Package length is shown in the second decimal place in millimeter. Package length DnomMinimum 0,50 Maximum 10,00 Tolerance vD 0,05 vDdenotes tolerance. Package width E Package width is shown in the second decim
34、al place in millimeter. Package width EnomMinimum 0,50 Maximum 10,00 Tolerance vE 0,05 -MD, MEvEdenotes tolerance. Profile height A When A 0,65, the tolerance of nominal height is 0,07. When 0,80 A 1,0, the tolerance of nominal height is 0,10. A shall not exceed 1,0. A includes package warpage and t
35、ilt allowances. Stand-off height A11) For S-FBGA: ebnommin nom max 0,80 0,50 0,35 0,40 0,45 0,80 0,45 0,30 0,35 0,40 0,65 0,40 0,28 0,330,38 0,50 0,30 0,20 0,25 0,30 0,40 0,25 0,15 0,20 0,25 0,30 0,20 0,10 0,15 0,20 For low stand-off S-FBGA: A1 0,20 2) For S-FLGA: A1 0,10 BS EN 60191-6-22:2013 10 60
36、191-6-22 IEC:2012 Table 1 (Continued) Dimensions in millimeters Term Symbol Specification Recommended value Notes Terminal pitch e e= 0,80 0,65 0,50 0,40 0,30 0,25 Terminal diameter b 1) For S-FBGA: emin nom max 0,80 0,45 0,50 0,55 0,80 0,40 0,45 0,50 0,650,35 0,40 0,45 0,50 0,25 0,30 0,35 0,40 0,20
37、 0,25 0,30 0,30 0,170,20 0,23 enom 0,80 0,50 0,65 0,40 0,50 0,30 0,40 0,25 0,30 0,20 2) For S-FLGA: eminnommax 0,80 0,35 0,40 0,45 0,65 0,28 0,33 0,38 0,500,20 0,25 0,30 0,40 0,15 0,20 0,25 0,30 0,12 0,15 0,18 0,25 0,10 0,13 0,16 Datum-based positional tolerance of terminals x1x1= 0,08 Relative posi
38、tional tolerance of terminals x2ex20,80 0,08 0,65 0,08 0,50 0,05 0,40 0,05 0,30 0,03 0,25 0,03 BS EN 60191-6-22:201360191-6-22 IEC:2012 11 Table 1 (Continued) Dimensions in millimeters Term Symbol Specification Recommended value Notes Coplanarity y ey 0,80 0,10 0,65 0,08 0,50 0,05 0,40 0,05 0,30 0,0
39、5 0,25 0,05 Parallelism of the top surface y1y1= 0,08 Number of terminals n n = ME MD(ME 1) MDME (MD 1) (ME 1) (MD 1) ME (E bmax vE x1 x2) /e+ 1 MD (D bmax vD x1 x2) /e+ 1 Numbers of matrices in MEand MDare shown in Table 3. Maximum matrix size in length MDMaximum matrix size in width ME7.2 Group 2
40、Group 2 dimensions are shown in Table 2. Table 2 Dimensions and tolerances of Group 2 Dimensions in millimeters Term Symbol Specification Recommended value Notes Overhang dimension in length ZDZD= Dnom (MD 1) e / 2 Reference value Overhang dimension in width ZEZE= Enom (ME 1) e / 2 Reference value D
41、atum-defined terminal- existence area b3b3= bmax+ x1 Relative terminal- existence area b4b4 = bmax+ x2 BS EN 60191-6-22:2013 12 60191-6-22 IEC:2012 8 Combination list of D, E, MD, and MECombination lists of D, E, MD, and MEare shown in the following Tables 3, 4, 5, 6, 7 and 8. Table 3 e= 0,80 mm pit
42、ch S-FBGA and S-FLGA BGA bmax= 0,55 BGA bmax= 0,50 LGA bmax= 0,45 D or E mm MD or MEMD 1 or ME 1 D or E mm MD or MEMD 1 or ME 1 D or E mm MD or MEMD 1 or ME 1 1,56 2,35 2 1,51 2,30 2 1,46 2,25 2 2,36 3,15 3 2 2,31 3,10 3 2 2,26 3,05 3 2 3,16 3,95 4 3 3,11 3,90 4 3 3,06 3,85 4 3 3,96 4,75 5 4 3,91 4,
43、70 5 4 3,86 4,65 5 4 4,76 5,55 6 5 4,71 5,50 6 5 4,66 5,45 6 5 5,56 6,35 7 6 5,51 6,30 7 6 5,46 6,25 7 6 6,36 7,15 8 7 6,31 7,10 8 7 6,26 7,05 8 7 7,16 7,95 9 8 7,11 7,90 9 8 7,06 7,85 9 8 7,96 8,75 10 9 7,91 8,70 10 9 7,86 8,65 10 9 8,76 9,55 11 10 8,71 9,50 11 10 8,66 9,45 11 10 9,56 10,35 12 11 9
44、,51 10,30 12 11 9,46 10,25 12 11 Table 4 e= 0,65 mm pitch S-FBGA and S-FLGA BGA bmax= 0,45 LGA bmax= 0,38 D or E mm MDor MEMD 1 or ME 1 D or E mm MDor MEMD 1 or ME 1 1,31 1,95 2 1,24 1,88 2 1,96 2,60 3 2 1,89 2,53 3 2 2,61 3,25 4 3 2,54 3,18 4 3 3,26 3,90 5 4 3,19 3,83 5 4 3,91 4,55 6 5 3,84 4,48 6
45、5 4,56 5,20 7 6 4,49 5,13 7 6 5,21 5,85 8 7 5,14 5,78 8 7 5,86 6,50 9 8 5,79 6,43 9 8 6,51 v7,15 10 9 6,44 7,08 10 9 7,16 7,80 11 10 7,09 7,73 11 10 7,81 8,45 12 11 7,74 8,38 12 11 8,46 9,10 13 12 8,39 9,03 13 12 9,11 9,75 14 13 9,04 9,68 14 13 9,76 10,40 15 14 9,69 10,33 15 14 BS EN 60191-6-22:2013
46、60191-6-22 IEC:2012 13 Table 5 e= 0,50 mm pitch S-FBGA and S-FLGA BGA bmax= 0,35 LGA bmax= 0,30 D or E mm MDor MEMD 1 or ME 1 D or E mm MDor MEMD 1 or ME 1 1,03 1,52 2 0,98 1,47 2 1,53 2,02 3 2 1,48 1,97 3 2 2,03 2,52 4 3 1,98 2,47 4 3 2,53 3,02 5 4 2,48 2,97 5 4 3,03 3,52 6 5 2,98 3,47 6 5 3,53 4,0
47、2 7 6 3,48 3,97 7 6 4,03 4,52 8 7 3,98 4,47 8 7 4,53 5,02 9 8 4,48 4,97 9 8 5,03 5,52 10 9 4,98 5,47 10 9 5,53 6,02 11 10 5,48 5,97 11 10 6,03 6,52 12 11 5,98 6,47 12 11 6,53 7,02 13 12 6,48 6,97 13 12 7,03 7,52 14 13 6,98 7,47 14 13 7,53 8,02 15 14 7,48 7,97 15 14 8,03 8,52 16 15 7,98 8,47 16 15 8,
48、53 9,02 17 16 8,48 8,97 17 16 9,03 9,52 18 17 8,98 9,47 18 17 9,53 10,02 19 18 9,48 9,97 19 18 9,98 10,47 20 19 BS EN 60191-6-22:2013 14 60191-6-22 IEC:2012 Table 6 e= 0,40 mm pitch S-FBGA and S-FLGA BGA bmax= 0,30 LGA bmax= 0,25 D or E mm MDor MEMD 1 or ME 1 D or E mm MDor MEMD 1 or ME 1 0,88 1,27 2 0,83 1,22 2 1,28 1,67 3 2 1,23 1,62 3 2 1,68 2,07 4 3 1,63
