1、BRITISH STANDARD BS IEC 61523-3:2004 Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the electronic design process ICS 35.240.50 BS IEC 61523-3:2004 This British Standard was published under the authority of the Standards Policy and Strategy Committee on 15 December 200
2、4 BSI 15 December 2004 ISBN 0 580 44887 8 National foreword This British Standard reproduces verbatim IEC 61523-3:2004 and implements it as the UK national standard. The UK participation in its preparation was entrusted to Technical Committee GEL/93, Design automation, which has the responsibility t
3、o: A list of organizations represented on this committee can be obtained on request to its secretary. Cross-references The British Standards which implement international publications referred to in this document may be found in the BSI Catalogue under the section entitled “International Standards C
4、orrespondence Index”, or by using the “Search” facility of the BSI Electronic Catalogue or of British Standards Online. This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. Compliance with a British Standard does
5、not of itself confer immunity from legal obligations. aid enquirers to understand the text; present to the responsible international/European committee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European develop
6、ments and promulgate them in the UK. Summary of pages This document comprises a front cover, an inside front cover, the IEC title page, pages 2 to 90, an inside back cover and a back cover. The BSI copyright notice displayed in this document indicates when the document was last issued. Amendments is
7、sued since publication Amd. No. Date CommentsINTERNATIONAL STANDARD IEC 61523-3 First edition 2004-09 IEEE 1497 Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the electronic design process Reference number IEC 61523-3(E):2004 IEEE Std. 1497(E):2001 BSIEC615233:2004 CON
8、TENTS FOREWORD. 3 IEEE Introduction. 71. Overview. 8 1.1 Scope. 8 1.2 Organization of this standard 8 2. References. 9 3. Conventions 9 3.1 Terminology conventions 9 3.2 Syntactic conventions 9 4. SDF in the design process. 12 4.1 Sharing of timing data. 12 4.2 Using multiple SDF files in one design
9、. 12 4.3 Timing data and constraints 13 4.4 Timing environments 13 4.5 Back-annotation of timing data for design analysis 13 4.6 Forward-annotation of timing constraints for design synthesis. 15 4.7 Timing models supported by SDF. 16 5. Defining the standard delay format. 18 5.1 SDF file content 18
10、5.2 Header section. 20 5.3 Cells 25 5.4 Delays 28 5.5 Timing checks. 46 5.6 Labels 60 5.7 Timing environment 62 Annex A (normative) Syntax of SDF . 74 Annex B (informative) SDF file examples . 84 Annex C (informative) List of Participants. 89 Pusilbdeh yb IEC uecil rednecn from 4002 .EEEI .EEEI lAr
11、listhg erdevres. BSIEC615233:20042INTERNATIONAL ELECTROTECHNICAL COMMISSION _ DELAY AND POWER CALCULATION STANDARDS Part 3: Standard Delay Format (SDF) for the electronic design process FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization co
12、mprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International St
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14、eparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two orga
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18、ional publication shall be clearly indicated in the latter. 5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any equipment declared to be in conformity with an IEC Publication. 6) Attention is drawn to the possibility that some of the elements of t
19、his IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC/IEEE 61523-3 has been processed through IEC technical committee 93: Design automation. The text of this standard is based on the follow
20、ing documents: IEEE Std FDIS Report on voting 1497 (2001) 93/191/FDIS 93/196/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives. The commit
21、tee has decided that the contents of this publication will remain unchanged until 2006. IEC 61523 consists of the following parts, under the general title Delay and power calculation standards: IEC 61523-1, Part 1: Integrated circuit delay and power calculation systems Psilbudeh yb IEC uecil rednecn
22、 from 4002 .EEEI .EEEI lAir lsthg erdevres. BSIEC615233:20043IEC 61523-2, Part 2: Pre-layout delay calculation specification of CMOS ASIC libraries IEC/IEEE 61523-3, Part 3: Standard Delay Format (SDF) for the electronic process Psilbudeh yb IEC uecil rednecn from 4002 .EEEI .EEEI lAir lsthg erdevre
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42、ednecn from 4002 .EEEI .EEEI lAir lsthg erdevres. BSIEC615233:20045 IEEE Standard for Standard Delay Format (SDF) for the Electronic Design ProcessSponsorDesign Automation Standards Committee of the IEEE Computer SocietyApproved 5 December 2001IEEE-SA Standards BoardAbstract:The Standard Delay Forma
43、t (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools,
44、 and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the formats contents will find it useful.Keywords:computer, computer languages, delay, delay backannotation, dig
45、ital systems, electron- ic systems, hardware, hardware design, SDF, timing, timing analysis, timing backannotation, timing verification Psilbudeh yb IEC uecil rednecn from 4002 .EEEI .EEEI lAir lsthg erdevres. BSIEC615233:20046 poCry.EEEI 1002 thgi r llAreser sthgiv.deiiiThe Standard Delay Format (S
46、DF) was designed to serve as a simple textual medium for communicating timing information and constraints between EDA tools. The original version was designed by Rajit C. Chan- dra in 1990 while at Cadence Design Systems, and was intended as a means of communicating macrocell and interconnect delays
47、 from Gate Ensemble to Verilog-XL, Veritime and other stand-alone tools requiring timing data. Because it was originally targeted for annotation to tools using the Verilog language, many SDF constructs are analogous to those in Verilog specify blocks. Those already familiar with the Verilog specify
48、block will nd many of the SDF constructs familiar, such as SETUP and PATHPULSE. SDF also includes constructs for annotating interconnect delays, and can be used for forward annotation by specifying path delay con- straints from timing analysis to oorplanners, and synthesis and layout tools. SDF was
49、rst introduced into the EDA marketplace in 1991 where it won quick acceptance. Cadence placed SDF in the public domain in 1992 when it turned control over to Open Verilog International (OVI), and OVI delivered the rst SDF standard, version 2.0, in June, 1993 (SDF version 1.0 was used by Cadence). OVI has since introduced version 2.1 in February, 1994, and version 3.0 in May, 1995. VHDL (IEEE 1076) also takes advantage of SDF through the VITAL standard.
