1、BRITISH STANDARD BSIEC 796-2:1990 Implementation of IEC796-2:1990 Microprocessor systembus 8-bit and16-bit data (MULTIBUS I) Part 2: Mechanical and pin descriptions for the system bus configuration, with edge connectors (direct)BSIEC796-2:1990 This British Standard, having been prepared under thedir
2、ectionof the InformationSystems TechnologyStandards Policy Committee, was published underthe authority of the Standards Board and comes into effect on 28 February1991 BSI 04-2000 The following BSI references relate to the work on this standard: Committee reference IST/6 Draft for comment 90/67535 DC
3、 ISBN 0 580 19345 4 Committees responsible for this British Standard The preparation of this British Standard was entrusted by the Information Systems Technology Standards Policy Committee (IST/-) to Technical Committee IST/6, upon which the following bodies were represented: Association for Payment
4、 Clearing Services British Computer Society British Telecommunications plc Business Equipment and Information Technology Association Department of Trade and Industry (Information Technology Standards Unit) Department of Trade and Industry (National Physical Laboratory) Electronic Engineering Associa
5、tion Electricity Supply Industry in England and Wales HM Treasury (Central Computer and Telecommunications Agency) Information Technology Users Standards Association Institute of Data Processing Management Inter-Universities Computing Committee Joint Network Team National Computing Centre Ltd. Natio
6、nal Health Service OFTEL (Office of Telecommunications) Post Office Telecommunications Engineering and Manufacturing Association Telecommunications Managers Association Amendments issued since publication Amd. No. Date CommentsBSIEC796-2:1990 BSI 04-2000 i Contents Page Committees responsible Inside
7、 front cover National foreword ii Foreword iii Text of IEC 796-2 1BSIEC796-2:1990 ii BSI 04-2000 National foreword This British Standard reproduces verbatim IEC796-2:1990 and implements it as the UK national standard. This British Standard is published under the direction of the Information Systems
8、Technology Standards Policy Committee whose Technical Committee IST/6 has the responsibility to: aid enquirers to understand the text; present to the responsible international committee any enquiries on interpretation, or proposals for change, and keep UK interests informed; monitor related internat
9、ional and European developments and promulgate them in the UK. For the purposes of this British Standard, any references to page numbers in the text should be ignored. NOTEInternational and European Standards, as well as overseas standards, are available from BSI Sales Department, BSI, Linford Wood,
10、 Milton Keynes, MK146LE. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages
11、 This document comprises a front cover, an inside front cover, pages i and ii, theIEC title page, pages ii to iv, pages1 to6 and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside fro
12、nt cover.BSIEC796-2:1990 ii BSI 04-2000 Contents Page Foreword iii Introduction 1 1 Scope 1 2 Object 1 3 Backplane considerations 1 3.1 Board to board relationships 1 3.2 System bus pin assignments 1 3.3 Bus connectors 1 4 Form factors 1 4.1 Connector naming and pin numbering standards 2 4.2 Standar
13、d outline of printed wiring boards 2 Figure 1 Backplane card to card separation 2 Figure 2 Typical backplane 3 Figure 3 Connector and pin numbering 3 Figure 4 Standard printed wiring board outline 4 Table I Pin assignment of bus signals on connector (P1) 5 Table II Pin assignment of bus signals on c
14、onnector (P2) 6BSIEC796-2:1990 BSI 04-2000 iii Foreword 1) The formal decisions or agreements of the IEC on technical matters, prepared by Technical Committees on which all the National Committees having a special interest therein are represented, express, as nearly as possible, an international con
15、sensus of opinion on the subjects dealt with. 2) They have the form of recommendations for international use and they are accepted by the National Committees in that sense. 3) In order to promote international unification, the IEC expresses the wish that all National Committees should adopt the text
16、 of the IEC recommendation for their national rules in so far as national conditions will permit. Any divergence between the IEC recommendation and the corresponding national rules should, as far as possible, be clearly indicated in the latter. 4) The IEC has not laid down any procedure concerning m
17、arking as an indication of approval and has no responsibility when an item of equipment is declared to comply with one of its recommendations. Preface This standard has been prepared by Sub-Committee47B 1) : Microprocessor systems, of IEC Technical Committee No.47: Semiconductor devices. This standa
18、rd forms Part2 of a series of publications, the other parts being: The text of this standard is based on the following documents: Full information on the voting for the approval of this standard can be found in the Voting Report indicated in the above table. 1) IEC Sub-Committee47B has now been tran
19、sferred to ISO/IEC JTC1. This standard was approved according to IEC procedures and is therefore published as an IEC standard. Publication796-1:1990: Microprocessor system bus8-bit and16-bit data (MULTIBUSI) Part1: Functional description with electrical and timing specifications. Publication796-3:19
20、90: Part3: Mechanical and pin descriptions for the Eurocard configuration with pin and socket (indirect) connectors. Six Months Rule Report on Voting 47B(CO)9 47B(CO)14iv blankBSIEC796-2:1990 BSI 04-2000 1 Introduction This standard is one of a series which deals with the electrical and mechanical i
21、nterfaces to allow various microprocessor system components to interact with each other. The interface bus serves as a parallel transfer and utility signal interconnect for closely coupled system components. The series consists of one functional description and two alternative mechanical standards.
22、1 Scope This standard is applicable to an interface used to connect microprocessor system components by means of the edge connector (direct) type backplane. 2 Object The object of this standard is to describe all the physical and mechanical specifications that a designer shall be concerned with when
23、 designing a backplane or when designing printed circuit boards that will plug into the system bus interface. All dimensions are in millimeters with inches added in parentheses for reference only. (Millimeter dimensions govern.) 3 Backplane considerations The maximum length of the backplane connecti
24、ng modules is457.2mm(18in). Extender boards used within the system will not be supported by the bus unless the overall resulting length of the bus including the extender card is less than the457.2mm maximum. 3.1 Board to board relationships The following printed circuit board specification shall be
25、adhered to when designing compatible boards which are to operate in a15.3mm(0.6in) board to board spacing backplane. a) Board to board spacing (L C ) Centre to centre of boards when plugged into backplane shall be at least15.24 0.51mm(0.6 0.02in). b) Board thickness (L T ) The typical board thicknes
26、s is1.575 0.128mm(0.062 0.005in). c) Component lead length (L L ) The length of the component leads below the printed circuit board cannot exceed2.362mm(0.093in). d) Component height (L H ) The following equation is used to determine the maximum height of the components above the printed circuit boa
27、rd: (L H )(L C )(L T )(L L ) (L H )14.73mm1.702mm2.362 mm (0.58in0.067in0.093in) (L H )10.67mm(0.420in) (including board warpage). Electrically conductive components require L Hto be decreased to10.16mm(0.40in). An example of a typical backplane and the components necessary to implement it are shown
28、 inFigure 2, page3. This standard contains only the mechanical specifications for designing a system bus interface. The designer shall also take into consideration the electrical specifications in Section 3 of IEC Publication796-1. 3.2 System bus pin assignments Printed circuit boards which are desi
29、gned to interface to the bus have two connectors which plug into the backplane, P1 (primary) and P2 (auxiliary). Table I shows the pin signal assignments for the P1 connector on the printed circuit boards. Reserved signals on the P1 connector shall be bussed as normal signal lines on the backplane.
30、Table II shows the pin signal assignments for the P2 connector on the printed circuit boards. If a backplane is used then the “reserved and bussed” signals shall be bussed as normal signal lines. 3.3 Bus connectors The backplane has connectors that mate to the P1(43/86 pin) board edge connector. The
31、 backplane uses43/86 pin on3.96mm(0.156in) centre connectors. The P2 connector is a30/60 pin board edge connector with2.54mm(0.1in) pin centres. 4 Form factors Certain characteristics of the bus shall be taken into consideration when designing printed circuit boards that interface to it. The designe
32、r will ensure himself of system bus compatibility if the specifications discussed in this standard are followed.BSIEC796-2:1990 2 BSI 04-2000 4.1 Connector naming and pin numbering standards The P1 and P2 connectors on the printed circuit boards designed for the system bus interface should comply wi
33、th the following requirements (seeFigure 2): a) The connectors on the bus side of the board shall be called P1 and P2. P1 is the86-pin main connector, and P2 is the60-pin auxiliary connector. b) Pins shall be numbered with odd numbers on the component side of the board, and in ascending order when g
34、oing counter-clockwise around the board (seeFigure 3, page3). 4.2 Standard outline of printed wiring boards Figure 4, page4, shows the standard outline for compatible boards (printed wiring boards and printed circuit boards). The non-bus edge of the board is not restricted. The remainder of the boar
35、d including connectors P1 and P2 shall adhere to the dimensions shown in Figure 4. Only the basic boards standard vertical height is currently specified. Figure 1 Backplane card to card separationBSIEC796-2:1990 BSI 04-2000 3 Parts list 1 PWS termination backplane 1 10 pin,1.1 k7,9 resistor,1.5 W re
36、sistor pack (RP6) 27 post wafer connectors(3.962mm pin centres) (J6J8) 1 1 k7 resistor,1/8 W, 5% (R1) 4 edge board connectors,43/86 pins on3.962mm centres (J2J5) 1 2.2 k7 resistor,1/8 W, 5% (R5) 2 220 7 resistors,1/4 W, 5% (R9, R11) 12 wire wrap posts 2 330 7 resistors,1/4 W, 5% (R10, R12) 4 10 pin,
37、2.2 k7,9 resistors,1.5 W resistor packs (RP1RP4) 2 510 7 resistors,1/8 W, 5% (R7, R8) 1 10 pin,1 k7,9 resistor,1.5 W resistor pack (RP5) Figure 2 Typical backplane Figure 3 Connector and pin numberingBSIEC796-2:1990 4 BSI 04-2000 Figure 4 Standard printed wiring board outlineBSIEC796-2:1990 BSI 04-2
38、000 5 Table I Pin assignment of bus signals on connector (P1) Pin Component side Pin Circuit side Mnemonic Description Mnemonic Description Power 1 GND Signal GND 2 GND Signal GND supplies 3 +5 V +5 V d.c. 4 +5 V +5 V d.c. 5 +5 V +5 V d.c. 6 +5 V +5 V d.c. 7 +12 V +12 V d.c. 8 +12 V +12 V d.c. 9 Res
39、erved, bussed 10 Reserved, bussed 11 GND Signal GND 12 GND Signal GND Bus 13 BCLK* Bus clock 14 INIT* Initialize controls 15 BPRN* Bus priority IN 16 BPRO* Bus priority OUT 17 BUSY* Bus busy 18 BREQ* Bus request 19 MRDC* Memory read command 20 MWTC* Memory write command 21 IORC* I/O read command 22
40、IOWC* I/O write command 23 XACK* XFER acknowledge 24 INH1* Inhibit 1 (disable RAM) Bus controls and address 25 LOCK* Lock 26 INH2* Inhibit2 (disable PROM or ROM) 27 BHEN* Byte high enable 28 A16* Address bus 29 CBRQ* Common bus request 30 A17* 31 CCLK* Constant clock 32 A18* 33 INTA* Interrupt ackno
41、wledge 34 A19* Interrupts 35 INT6* Parallel interrupt requests 36 INT7* Parallel interrupt requests 37 INT4* 38 INT5* 39 INT2* 40 INT3* 41 INT0* 42 INT1* Address 43 A14* Address bus 44 A15* Address bus 45 A12* 46 A13* 47 A10* 48 A11* 49 A8* 50 A9* 51 A6* 52 A7* 53 A4* 54 A5* 55 A2* 56 A3* 57 A0* 58
42、A1* Data 59 D14* Data bus 60 D15* Data bus 61 D12* 62 D13* 63 D10* 64 D11* 65 D8* 66 D9* 67 D6* 68 D7* 69 D4* 70 D5* 71 D2* 72 D3* 73 D0* 74 D1* Power 75 GND Signal GND 76 GND Signal GND supplies 77 Reserved, bussed 78 Reserved, bussed 79 12 V 12 V d.c. 80 12 V 12 V d.c. 81 +5 V +5 V d.c. 82 +5 V +5
43、 V d.c. 83 +5 V +5 V d.c. 84 +5 V +5 V d.c. 85 GND Signal GND 86 GND Signal GND NOTEAll reserved pins are reserved for future use and should not be used if upwards compatibility is desired.BSIEC796-2:1990 6 BSI 04-2000 Table II Pin assignment of bus signals on connector (P2) Pin Component side Pin C
44、ircuit side Mnemonic Description Mnemonic Description 1 Reserved, not bussed 2 Reserved, not bussed 3 Reserved, not bussed 4 Reserved, not bussed 5 Reserved, not bussed 6 Reserved, not bussed 7 Reserved, not bussed 8 Reserved, not bussed 9 Reserved, not bussed 10 Reserved, not bussed 11 Reserved, no
45、t bussed 12 Reserved, not bussed 13 Reserved, not bussed 14 Reserved, not bussed 15 Reserved, not bussed 16 Reserved, not bussed 17 Reserved, not bussed 18 Reserved, not bussed 19 Reserved, not bussed 20 Reserved, not bussed 21 Reserved, not bussed 22 Reserved, not bussed 23 Reserved, not bussed 24
46、Reserved, not bussed 25 Reserved, not bussed 26 Reserved, not bussed 27 Reserved, not bussed 28 Reserved, not bussed 29 Reserved, not bussed 30 Reserved, not bussed 31 Reserved, not bussed 32 Reserved, not bussed 33 Reserved, not bussed 34 Reserved, not bussed 35 Reserved, not bussed 36 Reserved, no
47、t bussed 37 Reserved, not bussed 38 Reserved, not bussed 39 Reserved, not bussed 40 Reserved, not bussed 41 Reserved, bussed 42 Reserved, bussed 43 Reserved, bussed 44 Reserved, bussed 45 Reserved, bussed 46 Reserved, bussed 47 Reserved, bussed 48 Reserved, bussed 49 Reserved, bussed 50 Reserved, bu
48、ssed 51 Reserved, bussed 52 Reserved, bussed 53 Reserved, bussed 54 Reserved, bussed Address 55 A22* Address bus 56 A21* Address bus 57 A20* 58 A23* 59 Reserved, bussed 60 Reserved, bussed NOTEAll reserved pins are reserved for future use and should not be used if upwards compatibility is desired. P
49、ins1 to40 are for “special use”. Special uses are defined in categories. Only category No.1 is currently described. Category No.1 is unconstrained use. Other categories are expected to include higher performance buses, I/O interfaces, etc. Pins41 to60 are intended for future address, data, and/or other P1 related signals.blankBSIEC 796-2:1990 BSI 389 Chiswick High Road London W4 4AL BSIBritishStandardsInstitution BSI is the independent national body responsible for preparing BritishStandards. It presen
