1、Documentation on designautomation subjects Mathematical algorithm hardware description languages for system level modeling and verification(HDLMath)PD IEC/TR 63051:2017BSI Standards PublicationWB11885_BSI_StandardCovs_2013_AW.indd 1 15/05/2013 15:06National forewordThis Published Document is the UK
2、implementation of IEC/TR 63051:2017.The UK participation in its preparation was entrusted to TechnicalCommittee EPL/501, Electronic Assembly Technology.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all th
3、e necessary provisions ofa contract. Users are responsible for its correct application. The British Standards Institution 2017.Published by BSI Standards Limited 2017ISBN 978 0 580 93916 7ICS 25.040.01; 35.240.50Compliance with a British Standard cannot confer immunity fromlegal obligations.This Pub
4、lished Document was published under the authority of the Standards Policy and Strategy Committee on 31 January 2017.Amendments/corrigenda issued since publicationDate Text affectedPUBLISHED DOCUMENTPD IEC/TR 63051:2017IEC TR 63051 Edition 1.0 2017-01 TECHNICAL REPORT Documentation on design automati
5、on subjects Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath) INTERNATIONAL ELECTROTECHNICAL COMMISSION ICS 25.040.01; 35.240.50 ISBN 978-2-8322-3772-4 Registered trademark of the International Electrotechnical Commission Warning! Make sure th
6、at you obtained this publication from an authorized distributor. colourinsidePD IEC/TR 63051:2017 2 IEC TR 63051:2017 IEC 2017 CONTENTS FOREWORD . 3 INTRODUCTION . 5 1 Scope 7 2 Normative references 7 3 Terms and definitions 7 4 Definition and positioning of HDLMath . 7 4.1 General . 7 4.2 Current H
7、DLMaths 7 4.3 Design abstraction level of HDLMath 8 5 Functional requirements of HDLMath . 9 5.1 General . 9 5.2 Mathematical expressions . 9 5.3 Various kinds of precision computation . 10 5.4 Exception and error handling 10 5.5 Multi-dimensional arrays . 11 5.6 Mathematical functions . 11 5.7 Mixe
8、d numerical and symbolic computations . 12 5.8 Feedback process . 12 5.9 User-defined functions in C-code 13 5.10 Verification environment . 14 6 Comparison of current HDLMath languages . 14 7 Conclusion 15 Bibliography 16 Figure 1 Numbers of description lines 9 Figure 2 Examples of mathematical exp
9、ressions 10 Figure 3 Multi-dimensional arrays and mathematical functions in HDLMath1 11 Figure 4 Multi-dimensional arrays and mathematical functions in HDLMath2 12 Figure 5 Mixed numerical and symbolic computations in HDLMath1 and HDLMath2 . 12 Figure 6 Example of a feedback process 12 Figure 7 Exam
10、ple of feedback process in HDLMath1 and HDLMath2 . 13 Figure 8 Examples of user-defined functions in C-code in HDLMath1 and HDLMath2 . 13 Figure 9 Structure of test-bench description of HDLMath1 and HDLMath2 . 14 Table 1 Examples of mathematics applications 5 Table 2 Examples of precision type 10 Ta
11、ble 3 Examples of overflow handling 11 Table 4 Comparison of current HDLMaths 15 PD IEC/TR 63051:2017IEC TR 63051:2017 IEC 2017 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ DOCUMENTATION ON DESIGN AUTOMATION SUBJECTS MATHEMATICAL ALGORITHM HARDWARE DESCRIPTION LANGUAGES FOR SYSTEM LEVEL MODELING AN
12、D VERIFICATION (HDLMath) FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerni
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23、ommittee may propose the publication of a Technical Report when it has collected data of a different kind from that which is normally published as an International Standard, for example “state of the art“. IEC 63051, which is a Technical Report, has been prepared by IEC technical committee 91: Elect
24、ronics assembly technology. The text of this Technical Report is based on the following documents: Enquiry draft Report on voting 91/1349/DTR 91/1396/RVC Full information on the voting for the approval of this Technical Report can be found in the report on voting indicated in the above table. This d
25、ocument has been drafted in accordance with the ISO/IEC Directives, Part 2. PD IEC/TR 63051:2017 4 IEC TR 63051:2017 IEC 2017 The committee has decided that the contents of this document will remain unchanged until the stability date indicated on the IEC website under “http:/webstore.iec.ch“ in the
26、data related to the specific document. At this date, the document will be reconfirmed, withdrawn, replaced by a revised edition, or amended. A bilingual version of this publication may be issued at a later date. IMPORTANT The colour inside logo on the cover page of this publication indicates that it
27、 contains colours which are considered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer. PD IEC/TR 63051:2017IEC TR 63051:2017 IEC 2017 5 INTRODUCTION Around the world, engineers in industries such as electronics and automo
28、biles are developing many kinds of systems and products. However, these are developed based on conventional design processes and suffer from many design problems and long design times. Because the laws of nature can be expressed mathematically, mathematics is a good algorithmic method for the descri
29、ption and modeling of such systems. Mathematical modeling is also an important approach for both solving problems and visualizing the abstract concepts involved. System LSI (Large Scale Integration) can be described at three levels of complexity as follows: 1) The the algorithmic level, which specif
30、ies only the algorithm used by the hardware for the problem solution; 2) the register transfer level, in which the registers are system elements and the data transfer between these registers is specified according to some rule; 3) the circuit level, where gates and flip-flops are replaced by the cir
31、cuit elements such as transistors, diodes, resistors, etc. For levels 2) and 3), VHDL (IEC 61691-1-1:2011 11) and SystemVerilog (IEC 62530:20112) have already been standardized by the IEC and IEEE and have been in practical use for over twenty years. For level 1), System C is able to describe hardwa
32、re systems at the behavioral level. The purpose of this document is to accelerate the standardization of a mathematical algorithm description language (HDLMath). HDLMath will be used to describe and verify the entire behavior of systems and/or products using mathematical algorithms of electronic sys
33、tems. It is a higher level language than conventional HDL (Hardware Description Language) languages such as VHDL and SystemVerilog. HDLMath and its design environment can support the design of many domains and applications as indicated in Table 1. Table 1 Examples of mathematics applications Mathema
34、tics Application examples Complex numbers Resistors, inductors, capacitors, power engineering, analysis of electric and magnetic fields, digital signal processing, image processing Matrices and determinants Electrical networks, computer graphics, image analysis Laplace transforms Circuits, power sys
35、tems (generators), feedback loops Statistics and probability Failure rates for semiconductor devices, behavior of semiconductor materials, image analysis, data compression, digital communications techniques, error correction Vector and trigonometry Oscillating waves (circuits, signal processing), el
36、ectric and magnetic fields, design of power generating equipment, radio frequency (RF) systems and antenna design Differentiation and integration Calculation of currents in a circuit, wave propagation, design of semiconductors, image analyses, design of firing circuits Functions, polynomial, linear
37、equations, logarithms, Euclidean geometry Curve fitting, fuel cell design, traffic modeling, power analysis, stress analysis, determining the size and shape of parts, software design, computer graphics _ 1Numbers in square brackets refer to the Bibliography. PD IEC/TR 63051:2017 6 IEC TR 63051:2017
38、IEC 2017 Recently, several HDLMath languages have already been used to design the mathematical algorithms in electronic systems. MATLAB/SIMULINK is one such popular design environment for the design and verification of various system behaviors. FinSimMath has been proposed and put to practical use b
39、y several groups to design and verify mathematical algorithms in ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). System C-AMS is mainly for analog circuit design and is an extension of the System C standardized by the IEEE and IEC. It is capable of describing
40、mathematical algorithms using additional C-code extensions. IEC TR 62856:2013 3 (BVDL, or Birds-eye View of Design Languages) describes the features of existing design languages, as well as listing the requirements for enhancing design languages and for developing new ones. Another purpose of this d
41、ocument is to add HDLMath to BVDL as a system modeling language. This document describes nine functional requirements for an HDLMath and compares current HDLMath languages from a design viewpoint. It is intended to accelerate the standardization of a mathematical algorithm design language and to est
42、ablish a good system modeling environment in the world. PD IEC/TR 63051:2017IEC TR 63051:2017 IEC 2017 7 DOCUMENTATION ON DESIGN AUTOMATION SUBJECTS MATHEMATICAL ALGORITHM HARDWARE DESCRIPTION LANGUAGES FOR SYSTEM LEVEL MODELING AND VERIFICATION (HDLMath) 1 Scope A hardware description language prov
43、ides a means to describe the behavior of a system precisely and concisely. This document describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algo
44、rithm design language and to help establish a new and good system modeling and verification environment. 2 Normative references The following documents are referred to in the text in such a way that some or all of their content constitutes requirements of this document. For dated references, only th
45、e edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. There are no normative references in this document. 3 Terms and definitions No terms and definitions are listed in this document. ISO and IEC maintain terminological dat
46、abases for use in standardization at the following addresses: IEC Electropedia: available at http:/www.electropedia.org/ ISO Online browsing platform: available at http:/www.iso.org/obp 4 Definition and positioning of HDLMath 4.1 General HDLMath is defined as a language for describing and verifying
47、the behavior of an entire system or product using mathematical algorithms. IEC TR 62856:2013 (BVDL) describes the features of existing design languages used in the design processes applied to the development of System-on-Chip (SoC) devices, which range from system level design, IP block creation and
48、 analog block design, to SoC design implementation and verification. HDLMath will cover system level design in the BVDL schema. 4.2 Current HDLMaths Currently, there are three kinds of language for these design environments: HDLMath1, HDLMath2, and HDLMath3. HDLMath1 is a kind of high-level language
49、 that has an interactive environment for numerical computation, visualization, and programming. It is able to analyze data, develop algorithms, and create models and applications using the language, tools, and built-in mathematical functions. It features the following: PD IEC/TR 63051:2017 8 IEC TR 63051:2017 IEC 2017 a) a block diagram environment for multi-domain simulation and model-based design; b) simulation, automatic code generation, and continuous te
