1、BRITISH STANDARD BS QC 760001:1994 IEC748-20-1: 1994 Harmonized system of quality assessment for electronic components Film and hybrid integrated circuits Generic specification Section1:Requirements for internal visual inspectionBSQC760001:1994 This British Standard, having been prepared under the d
2、irectionof the Electronic Components Standards Policy Committee, was published underthe authority of the Standards Board and comes intoeffect on 15 October1994 BSI08-1999 The following BSI references relate to the work on this standard: Committee reference ECL/24 Special announcement in BSINews, May
3、1994 ISBN 0 580 23468 1 Committees responsible for this British Standard The preparation of this British Standard was entrusted by the Electronic Components Standards Policy Committee (ECL/-) to Technical Committee ECL/24, upon which the following bodies were represented: Federation of the Electroni
4、cs Industry GAMBICA (BEAMA Ltd.) Ministry of Defence National Supervising Inspectorate Society of British Aerospace Companies Limited Amendments issued since publication Amd. No. Date CommentsBSQC760001:1994 BSI 08-1999 i Contents Page Committees responsible Inside front cover National foreword iii
5、1 Scope and object 1 1.1 Purpose 1 1.2 Sequence of inspections 1 1.3 Inspection apparatus 1 1.4 Inspection environment 1 1.5 Magnification 1 1.6 Definitions 1 1.7 Interpretations 2 1.8 Alternative test methods 2 2 Substrate and processes Low magnification 2 2.1 Substrate 2 2.2 Processes 2 3 Assembly
6、 Mechanical attachment and electrical connection ofparts tothe substrate 4 3.1 Added components 4 3.2 Assembly method Low magnification 4 4 Assembly Mechanical attachment and electrical connection of substrate to package Low magnification 5 4.1 General 5 4.2 Soldering and organic adhesive 5 5 Wire i
7、nterconnections 5 5.1 General 5 5.2 Gold ball and wedge bonds 5 5.3 Gold ball bonds 5 5.4 Tail-less (crescent) bonds 5 5.5 Wedge bonds 5 5.6 Compound bonds 6 5.7 Beam lead bonds 6 5.8 Criteria for wires 6 6 Package conditions 6 7 Foreign material 6 Figure 1 6 Figure 2 6 Figure 3 7 Figure 4 7 Figure
8、5 7 Figure 6 7 Figure 7 7 Figure 8 7 Figure 9 7 Figure 10 8 Figure 11 8 Figure 12 8 Figure 13 8 Figure 14 8 Figure 15 8BSQC760001:1994 ii BSI 08-1999 Page Figure 16 8 Figure 17 9 Figure 18 9 Figure 19 9 Figure 20 9 Figure 21 9 Figure 22 9 Figure 23 9 Figure 24 9 Figure 25 10 Figure 26 10 Figure 27 1
9、0 Figure 28 10 Figure 29 10 Figure 30 11 Figure 31 11 Figure 32 11 Figure 33 11 Figure 34 11 Figure 35 11 Figure 36 11 Figure 37 11 Figure 38 12 Figure 39 12 Figure 40 12 Figure 41 12 Figure 42 12 Figure 43 12 Figure 44 13 Figure 45 13 Figure 46 13 Figure 47 14 Figure 48 14 Figure 49 14 Figure 50 14
10、 Figure 51 15 Figure 52 15 Figure 53 15 Figure 54 15 Figure 55 15 Figure 56 16 Figure 57 16 Figure 58 17 Figure 59 Beam lead bond area 18 Figure 60 Beam lead bond location 18BSQC760001:1994 BSI 08-1999 iii National foreword This British Standard has been prepared under the direction of the Electroni
11、c Components Standards Policy Committee. It is identical with IEC748-20-1:1994 (QC760001) Semiconductor devices Integrated circuits Part20: Generic specification for film integrated circuits and hybrid film integrated circuits Section1: Requirements for internal visual examination, published by the
12、International Electrotechnical Commission (IEC), and is a harmonized specification in the IECQ system of quality assessment for electronic components. IEC748-20-1 was prepared by IEC Subcommittee47A, Integrated circuits, of IEC Technical Committee No.47, Semiconductor devices, and the UnitedKingdom
13、participation in the drafting was provided by SubcommitteeECL/24/4, Film and hybrid integrated circuits, of TechnicalCommittee ECL/24, Semiconductors. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their corre
14、ct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an inside front cover, pagesi toiv, pages1to18 and a back cover. This standard has been updated (see copyright date) and may have had
15、amendments incorporated. This will be indicated in the amendment table on the inside front cover.iv blankBSQC760001:1994 BSI 08-1999 1 1 Scope and object 1.1 Purpose The purpose of these examinations is to check the internal materials, construction and workmanship of film and hybrid integrated circu
16、its (F and HFICs). These examinations will normally be used prior to tapping or encapsulation to detect and eliminate the F and HFICs with internal defects that could lead to device failure in normal application. Other acceptance criteria may be agreed upon with the purchaser or supplier. 1.2 Sequen
17、ce of inspections The order in which inspections are presented is not a required order of examination and may be varied at the discretion of the manufacturer. Any aspect which may be obscured by a subsequent assembly process shall be examined before that process. 1.3 Inspection apparatus The apparat
18、us for this test shall include optical equipment capable of the specified magnification(s) and any visual standard (gauges, drawings, photographs, etc.) necessary to perform an effective examination and enable the operator to make objective decisions as to the acceptability of the device being exami
19、ned. Adequate fixtures shall be provided for handling devices during examination to promote efficient operation without inflicting damage to the units. 1.4 Inspection environment Under consideration. 1.5 Magnification “High magnification”(100 to200) inspection is normally performed with a microscope
20、 perpendicular to the relevant surface with the device under illumination. “Low magnification”(10 to100) inspection is normally performed with a monocular, a binocular or a stereomicroscope at an appropriate angle and illumination. 1.6 Definitions For the purposes of this section of IEC748-20, the f
21、ollowing definitions apply. 1.6.1 active circuit area all areas of functional circuit elements, operating metallization or any connected combinations thereof 1.6.2 multi-layer metallization (for conductors) two or more layers of metal or any other material used for interconnections that are not isol
22、ated from each other 1.6.3 edge metallization metallization that electrically connects different layers of metallization on or within a substrate at its edge 1.6.4 foreign material any material not used in the manufacture of the microcircuit or any in-built material that is displaced from its origin
23、al or intended position within the microcircuit package. Foreign material that appears opaque under those conditions of lighting and magnification used in routine visual inspection is considered as conductive 1.6.5 protective layer (passivation) layer of insulating material that protects part or all
24、 of the substrate area, including metallization, but excluding connecting pads, for example glassivation, solder resist, etc. 1.6.6 isolating layer layer used to isolate separate conductive or resistive levels 1.6.7 kerf slit or cut made by a material-removing process (forexample laser or abrasive t
25、rimming) 1.6.8 multilevel metallization (for conductors) two or more levels of metal or any other material used for interconnections that are isolated from each other by a grown or deposited insulating material and interconnected for example by vias or edge metallization 1.6.9 bond pad area that are
26、a of exposed metallization which is not covered by passivation 1.6.10 compound bond bonding of one bond on top of another bond 1.6.11 through-hole metallization metallization that electrically connects different levels of metallization on or within a substrate via a hole or holes 1.6.12 scratch any
27、tearing defect on the surface of a layerBSQC760001:1994 2 BSI 08-1999 1.6.13 cosmetic scratch shallow scratch which may extend completely across a layer and which does not expose or damage underlying layers, or laterally displace metallization beyond the edge of the conductor for example by mechanic
28、al deformation 1.6.14 void any defect in a layer not caused by a scratch where underlying material is visible 1.7 Interpretations Reference herein to “that exhibits” is considered satisfied when the visual image or visual appearance of the device under examination indicates a specific condition is p
29、resent. This does not require confirmation by any other method of testing. 1.8 Alternative test methods Visual examination requirements given below are not necessarily the only methods which can be used. However, the manufacturer should satisfy the National Authorized Institution (NAI) that any alte
30、rnative method will give equivalent assurance, otherwise the specified method is to be used. 2 Substrate and processes Low magnification 2.1 Substrate No device shall be acceptable that shows the following: holes through the substrate, except through lead holes, used or unused component mounting hol
31、es, or alignment holes; any crack that exceeds0,125mm in length and point toward an operating portion of the circuit (see Figure 1); any chip out that reduces any active (metallized) circuit area (see Figure 2); any crack that comes closer than0,025mm to an operating portion of the circuit (see Figu
32、re 3); any substrate having attached portions of another substrate that exceed the substrate dimensions allowed by the assembly drawing (seeFigure 4); any substrate having a section broken out around any substrate mounting hole greater than25% of the mounting hole circumference when designed for sub
33、strate to post attachment (see Figure 5); any crack that originates at an edge (seeFigure 6). 2.2 Processes 2.2.1 Conductors No device shall be acceptable that shows the following: 1) metallization scratches (a scratch is any tearing effect, including probe marks, in the surface of the metallization
34、); scratch in the metallization excluding bonding pads that exposes the substrate or underlying dielectric anywhere along its length and leaves less than50% of the metal width undisturbed (see Figure 7); scratch in multilayered metallization that exposes the underlying metal anywhere along its lengt
35、h and leaves less than50% of the top layer metal width undisturbed (see Figure 8); scratch in the bonding pad or fillet area that exposes the underlying dielectric or substrate and reduces the metallization path width connecting the bond to the inter connecting metallization to less than50% of the n
36、arrowest entering interconnect metallization stripe width. If two or more strips enter a bonding pad, each shall be considered separately (see Figure 9); 2) metallization voids void(s) in metallization except for wire or beam lead bonding pads that leaves less than50% of the metal width undisturbed
37、(seeFigure 7); void(s) in the wire or beam lead bonding pad area that leaves an area less than twice the maximum allowable bond size undisturbed; void(s) in the wire or beam lead bonding pad, including fillet area that reduces the metallization path width connecting the bond to the interconnecting m
38、etallization to less than50% of the narrowest entering interconnect metallization strip width (seeFigure 9). NOTEIf two or more strips enter a bonding pad, each should be considered separately. 3) metallization corrosion any metallization corrosion (see Figure 10); 4) metallization adherence any met
39、allization lifting, peeling or blistering (see Figure 11); 5) metallization probing (criteria contained in1) and2) shall apply as limitations on probing damage);BSQC760001:1994 BSI 08-1999 3 6) metallization bridging protrusion or expansion of the conductor that reduces the existing separation from
40、another element to less than25% or to less than50% of the minimum insulation distance specified in the design rules, whichever is the greater (see Figure 12); 7) metallization alignment misalignment where the conductor overlap is less than50% of the width of the narrower conductor (see Figure 13); 8
41、) foreign material particle of foreign material with any dimension greater than50% of the conductor width (see Figure 14). 2.2.2 Isolating layer No device shall be acceptable that shows the following: scratch or void at or over a dielectric step (seeFigure 15); any misalignment in cross-overs where
42、the dielectric is not visible on each side more than50% of the minimum designed insulation distance between circuit elements (seeFigure 16); a scratch, a nick or a void that exposes the buried conductor (see Figure 17); blistering or crazing (see Figure 18); any dielectric material covering more tha
43、n25% of a bonding or soldering area (seeFigure 19); permanent particle or foreign material with any dimension greater than50% of the buried element width (see Figure 20). 2.2.3 Resistors 2.2.3.1 Untrimmed resistors No device shall be acceptable that shows the following: a scratch, a nick or a void w
44、ith any dimension greater than50% of the width (see Figure 21); lifting, peeling or blistering (see Figure 22); protrusion or expansion of the resistor that reduces the existing separation from another element to less than25% or to less than50% of the minimum insulation distance specified in the des
45、ign rules, whichever is the greater (see Figure 23); particle of foreign material with any dimension greater than50% of the resistor width (seeFigure 24). Trimming shall not touch foreign particles; misalignment in the length direction of a resistor/conductor overlap greater than50% (seeFigure 25);
46、misalignment in the width direction outside the boundaries of the conductor pattern; any sharp change in colour of the resistor material within the resistor/conductor termination. 2.2.3.2 Trimmed resistors No device shall be acceptable that shows failures as described in2.2.3.1 or the following: 1)
47、abrasion trimmed resistors the minimum resistor width remaining after trimming shall be40% (see Figure 26), except where it can be shown that the maximum current density permitted by the design rules are not exceeded; width of the termination reduced by more than50% (see Figure 27); bridging of the
48、trim-cut (see Figure 28); a scratch, nick or void opposite a trim kerf which reduces the resistors width to40% (seeFigure 29); micro cracking and ragged edges in the resistor material (see Figure 30); residue of resistor material in the trim-cut (see Figure 31); 2) laser trimmed resistors the minimu
49、m resistor width remaining after trimming shall be40% (see Figure 26), except where it can be shown that the maximum current density permitted by the design rules are not exceeded; bridging of the trim-cut unless required by the design (see Figure 34); a scratch, nick or void, in combination with a trim in accordance with requirement above on minimum undisturbed resistor width (seeFigure 35); micro-cracking (see Figure 36); ragged edges in the resistor material (seeFigure 37)
