1、. - CECC CECCtSO*LO4- OL3*ISSUE*2 * = I1774497 0044133 AT4 M N ED E R LAN DS E LE KTROTECH N ISCH COMITE POSTBOX 5059 2600 GB DELFT This specification is also available from Nederlandse Philips Bedrijven B.V. ELECTRONIC COMPONENTS OF ASSESSED QUALITY IN ACCORDANCE WITH: GS: CECC 90 O00 Issue 3. SS:
2、CECC 90 100 Issue 3. FS: CECC 90 104 Issue 2. CECC 90 104-013 ISSUE 2 Page 1 I Total number of pages: 9 Detail Spec: N L-CECC 90 104-01 3 Issue : 2 Issued: December 1989 OUTLINE AND DIMENSIONS: IEC 191-2 I 050 G09/A76 G1 TE RMI NAC CONNECTIONS: See item 1.3 of this specification DETAIL SPECIFICATION
3、 FOR DIGITAL INTEGRATED CIRCUITS IN ACCORDANCE WITH FS 90 104 HEC/HEF4015B Dual 4-bit static shift register TYPICAL CONSTRUCTION: Si I icon mono1 i th ic local ox idation CMOS integrated circuit, cavity/non- cavity packages. CAUTION: STATIC SENSITIVE DEVICE I ASSESSMENT LEVELS: P, Y, L REMARKS Infor
4、mation about manufacturers who have components qualified to this detail specification is available in the current CECC O0 200: Qualified Products List. 8 L 1 Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted
5、 without license from IHS-,-,-Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft n 2 3 4 This specification is also available from Nederlandse Philips Bedrijven B.V. inputs outputs CP D MR 00 O1 O2 1JDiLDiXX J D2 L D2 Di X I D3 L D3 D2 Di J D4 L D4 D3 D2 -LXL no change Page 2 X of 9 X H LI
6、L L CECC 90 104-013 ISSUE 2 1 TYPE DESCRIPTION 1.1 Function The HEC/HEF40158 are dual edge-triggered 4-bit static shift registers (serial-to-parallel converters). Each shift register has a serial data input (DI, a clock input (CP), four fully buffered parallel outputs (O0 to 03) and an overriding as
7、ynchronous master reset input (MR). Information present on D is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to- HIGH transition of CP. A HIGH on MR clears the register and forces 00 to O3 to LOW, independent of CP and D. Sc
8、hmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 1.1.1 Function tables H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial 1 = positive-going transition = negative-going transition
9、Dn = either HIGH or LOW n = number of clock pulse transitions Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft This
10、specification is also available from Nederlandse Philips Bedrijven B.V. 1.1.2 Functional diagram Page 3 of 9 SHIFT R EG I ST E R 4-BITS MRA I ?f 2A 3 3A 10 t DB OOB 13 SHIFT O1B 12 cpB, REGISTER 02 11 4-BITS ,3B 2 MRB I A 7269526.2 Fig. 1 Functional diagram. 1.1.3 Pinning information DAI DB serial d
11、ata input MRAl MRB CPAI CPB OOA, OA, OA, OJA OOB, 01 B, 02B, OB master reset input (active HIGH) clock input ( LOW-to-HIGH edge-triggered) parallel outputs parallel outputs CECC 90 104-013 ISSUE 2 Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for Resale
12、No reproduction or networking permitted without license from IHS-,-,-r Nederlands Elektrotechnisch Comite Page 4 Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. of 9 Fig. 2 Logic diagram (one register). a CECC 90 104-013 ISSUE 2 1.3 Terminal ide
13、ntification, type designation and marking 1.3.1 Terminal identification (top view) b H E C/H E F40 1 5B I Fig. 3 Pinning diagram. 1.3.2 Type designation HEF = limited temperature range HEC = full temperature range. 1.3.3 Marking See item 2.5 and 2.6 of CECC 90 000. Copyright CENELEC Electronic Compo
14、nents Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. Page 5 of 9 CECC 90 104-
15、013 ISSUE 2 1.4 Ordering information When ordering please state the following: a : Quantity b : Manufacturer c : Operating ambient temperature range (HEC or HEF) and device number d : Quality assessment level (P, Y or L) e : Optional, screening class (refer to CECC 90 000) f : Package code (P = plas
16、tic, D = ceramic and T = mini-pack). 1.4.1 Ordering information example a : N (N = quantity required) b : Philips c : HEFXXX (XXX = device number) d:P e:B f :T. 2 Additional to clause 1 of FS 90 104. LIMITING CONDITIONS (not for inspection purposes) 2.1 Maximum continuous current into any output I =
17、 10 mA. 2.2 Maximum power dissipation per output Pmax = 100 mW. 2.3 Maximum power dissipation per package Temperature range: limited (for plastic and ceramic DI L) for Tamb = -40 to 70 Oc for Tamb = + 70 to + 85 Oc Temperature range: full (ceramic DI L only) for Tarnt, = -55 to 70 Oc for Tamb = +70
18、to 125 OC Temperature range: limited (for plastic SO) for Tamb = -40 to + 70 Oc for Tamb = i- 70 to i- 85 Oc Ptot ( max) = 500 m W. Derate linearly with 8 mW/K. Ptot (max) = 500 mW. Derate linearly with 8 mW/K. Ptot (max) = 400 mW. Derate linearly with 6 mW/K. 2.4 Transient energy rating 400 V. Copy
19、right CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*90*L04- OL3*ISSUE*2 tf D L4499 0044138 386 D parameter VDD symbol low I I I i Nederlands Elektrotechnisch Comite Postbox 5
20、059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. Page 6 of 9 CECC 90 104-013 ISSUE 2 a 3 Additional to clause 2 of FS 90 104. RECOMMENDED OPERATING CONDITIONS AND ASSOCIATED CHARACTERISTICS 3.1 Recommended operating conditions Applicable IODA category (it
21、em 2.1) : MSI. 3.2 Static and dynamic characteristics 3.2.1 Static characteristics In compliance with item 2.6, note 3 of FS 90 104. 1 I I I Output (source) current HI G H Output (source) current H I G H v- 5 10 15 5 10 15 min. -0,5 1 -1,3 -3,4 444 -1,l -3,O high min. -0,36 -0,9 -2,4 -0,36 49 -2,4 -
22、 unit - mA mA mA mA mA mA - conditions Vo = 4,6 V; VI = O or 5 V Vo = 93 V; VI = O or 10 V J 1 Tamb Vo= 13,5V;V1=Oor15V VO = 9,s V; VI = 0 or IO v Vo = 4,6 V; VI = Oor 5 V Vo = 13,5 V; VI = O or 15 V Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for Res
23、aleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*qO*L04- OL3*ISSUE*Z * m L974499 0044339 212 m This specification is also available from Nederlandse Philips Bedrijven B.V. 1 I 1 1 of 9 ISSUE 2 Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft Page 7 CECC 9
24、0 104-013 3.2.2 Dynamic characteristics Vss = 0 V; Tamb = +25 OC; CL = 50 pF; input transition times 20 ns; load circuit: see 2.13 family specification; temperature range: full and limited. parameter Propagation delays HIGH to LOW CP - On LOW to HIGH MR -0, HIGH to LOW Output transition times HIGH t
25、o LOW LOW to HIGH Set-up t me D - CP Hold time D -CP Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery ti m e for MR Maximum clock pulse frequency DD V 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 symbol PH L t LH tPH L TH L TLH %U thold
26、tWCPL WMRH RMR fmax min. 25 25 20 40 20 15 60 30 20 80 30 24 50 30 20 7 15 22 130 55 40 120 55 40 105 45 35 60 30 20 60 30 20 -1 5 -1 o -5 20 10 8 30 15 10 40 15 12 20 10 5 15 30 44 max. 260 110 80 240 110 80 21 o 90 70 120 60 40 120 60 40 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns n
27、s ns ns ns ns ns ns ns ns ns ns ns MHz M Hz MHz - typical extrapolation formula 103 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + i0,16 ns/pF) CL 93 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns+ (0,16 ns/pF) CL 78 ns + (0,55 ns/pF C L 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 10 n
28、s + (1,O ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns+ (1,O ns/pF) CL see waveforms Figs 4 and 5 Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitt
29、ed without license from IHS-,-,-CECC CECC+SO*104- O13+ISSUE*2 t* 1774499 0044140 T34 Page 8 of 9 Nederlands Elektrotechnisch Comite Postbox 5059 2600G6 Delft CECC 90 104-013 ISSUE 2 This specification is also available from Nederlandse Philips Bedrijven B.V. 3.2.2 Dynamic characteristics (continued)
30、 CP INPUT D INPUT 50 Olo -4 t,“ hold If -B 50 lo hold 1 4- 7269697.: Fig. 4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values. MR INPUT -ooh 1 i 1- t WMRH -if t RMR -, CP INPUT OUTPUT 7
31、269695 Fig. 5 Waveforms showing recovery time for MR and minimum MR puise width. Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Nederlands Elektrotechnisch Comite Postbox 5059
32、 2600GB Delft 1 VFD 1 typical formula for P (pw) This specification is also available from Nederlandse Philips Bedrijven B.V. where fi = input freq. (MHz) Page 9 of 9 c I fo = output freq. (MHz) Dynamic power 5 1 500fi + Zi(f,CL) x VDD CL = load capacitance (pF) dissipation per 10 6300 fi + Zi(f,CL)
33、 x VDD C(foCL) = sum of outputs package (P) 15 17000fi + Zi(foCL) x VDD VDD =supply voltage (V) 3.2.3 Supplementary dynamic characteristics Vss = 0 V; Tamb = 25 OC; CL = 50 pF; input transition times 20 ns. CECC 90 104-013 ISSUE 2 parameter Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
