1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct lead finish on last page. Update boilerplate. - CFS 05-11-01 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-06-04 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME CO
2、LUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFE
3、NSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, CMOS, 12-BIT, ANALOG-TO-DIGITAL CONVERTER, MONOLITHIC SILICON 02-12-12 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03609 REV B PAGE 1 OF 28 A
4、MSC N/A 5962-V060-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a hi
5、gh performance linear-digital microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item
6、on the engineering documentation: V62/03609 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 THS1206-EP CMOS, 12-bit, 6 MSPS, analog-to-digital converter 1.2.2 Case outline(s). The case outl
7、ines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 32 MO-153 Plastic thin shrink small outline package with gull wing leads 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish design
8、ator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B
9、 PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range: DGND to DVDD. -0.3 V to 6.5 V BGND to BVDD. -0.3 V to 6.5 V AGND to AVDD. -0.3 V to 6.5 V Analog input voltage range AGND 0.3 V to AVDD+ 1.5 V Reference input voltage . -0.3 V + AGND to AVDD+ 0.3 V Digital input voltage range -0.3 V to B
10、VDD/ DVDD+ 0.3 V Power dissipation (PD) (TA 25C) 1453 mW 2/ Operating virtual junction temperature range (TJ) -55C to +150C Storage temperature range -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . 260C 1.4 Recommended operating conditions. 3/ Power supply section Supply
11、 voltage: AVDD. 4.75 V to 5.25 V DVDD. 3 V to 5.25 V BVDD. 3 V to 5.25 V Analog and reference inputs section Analog input voltage in single-ended configuration VREFMto VREFPCommon-mode input voltage VCMin differential configuration 1 V to 4 V External reference voltage, VREFP. AVDD 1.2 V maximum Ext
12、ernal reference voltage, VREFM. 1.4 V minimum Digital inputs section High-level input voltage (VIH): With BVDD= 3.3 V 2 V minimum With BVDD= 5.25 V 2.6 V minimum Low-level input voltage (VIL) With BVDD= 3.3 V 0.6 V maximum With BVDD= 5.25 V 0.6 V maximum Input CONV_CLK frequency, (with DVDD= 3 V to
13、5.25 V) 0.1 MHz to 6 MHz CONV_CLK pulse duration, clock high, tW(CONV_CLKH): With DVDD= 3 V to 5.25 V . 80 ns to 5000 ns CONV_CLK pulse duration, clock low, tW(CONV_CLKL): With DVDD= 3 V to 5.25 V . 80 ns to 5000 ns Ambient operating temperature (TA) . -55C to +125C 1/ Stresses beyond those listed u
14、nder “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditio
15、ns for extended periods may affect device reliability. 2/ The derating factor above TA= +25C is 11.62 mW/C. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for pro
16、duct used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIA
17、TION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be
18、 permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with
19、 items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical
20、 dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Timing wave
21、forms. The timing waveforms shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B PAGE 5 TABLE I. Electrical performance chara
22、cteristics. 1/ Test Symbol Conditions -55C TA +125C Limits Unit Min Max Digital input section High-level input current IIHDVDD= digital inputs -50 50 A Low-level input current IILDigital input = 0 V -50 50 A Input capacitance CIN5 TYP pF High-level output voltage VOHIOH= -50 A, BVDD= 3.3 V BVDD 0.5
23、V IOH= -50 A, BVDD= 5 V BVDD 0.5 Low-level output voltage VOLIOL= 50 A, BVDD= 3.3 V 0.4 V IOL= 50 A, BVDD= 5 V 0.4 High-impedance-state output current IOZCS1 = DGND, CS0 = DVDD-10 10 A Output capacitance COUT5 TYP pF Load capacitance at databus D0 D11 CL30 pF Resolution RES 12 Bits Integral nonlinea
24、rity INL 1.8 LSB Differential nonlinearity DNL 1 LSB Offset error 2/ OE After calibration in differential mode -20 20 LSB After calibration in single-ended mode 20 TYP Gain error 2/ GE -20 20 LSB Analog input section Input capacitance CIN15 TYP Input leakage current IINLVAIN= VREFMto VREFP10 A Inter
25、nal voltage reference section Accuracy VREFP3.3 3.7 V VREFM1.3 1.7 V REFOUT 2.3 2.7 V Temperature coefficient TC 50 TYP PPM/C Reference noise RN 10 TYP V Power supply section Analog supply current IDDAAVDD= 5 V, BVDD= DVDD= 3.3 V 40 mA Digital supply current IDDD1 mA Buffer supply current IDDB4 mA S
26、upply current in power-down mode IDD P10 mA Power dissipation PD216 mW Power dissipation In power down PD30 TYP mW See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CO
27、DE IDENT NO. 16236 DWG NO. V62/03609 REV B PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions -55C TA +125C Limits Unit Min Max AC section Signal-to-noise ratio + distortion 3/ SINAD Differential mode 63 dB Single-ended mode 4/ 64 TYP Signal-to-noise ratio 3/
28、 SNR Differential mode 64 Single-ended mode 4/ 68 TYP Total harmonic distortion 3/ THD Differential mode -67 Single-ended mode -68 TYP Effective number of bits ENOB (SNR) Differential mode 10.17 Bits Single-ended mode 4/ 10.4 TYP Spurious free dynamic range 3/ SFDR Differential mode 67 dB Single-end
29、ed mode 69 TYP Analog input section Full power bandwidth with a source impedance of 150 in differential configuration FS sinewave, -3 dB 96 TYP MHz Full power bandwidth with a source impedance of 150 in single ended configuration FS sinewave, -3 dB 54 TYP Small signal bandwidth with a source impedan
30、ce of 150 in differential configuration 100 mVpp sinewave, -3 dB 96 TYP Small signal bandwidth with a source impedance of 150 in single ended configuration 100 mVpp sinewave, -3 dB 54 TYP Timing specification section Delay time td(DATA_AV)ns Delay time td(o)Latency tpipeCONV CLK Timing section Clock
31、 cycle of the internal clock oscillator 5/ tC159 175 ns Pulse width, CONVST 5/ t1 1 analog input 1.5 x tC2 analog input 2.5 x tC3 analog input 3.5 x tC4 analog input 4.5 x tCAperture time tdA1 TYP Time between consecutive start of single conversion 5/ t21 analog input 2 x tC2 analog input 3 x tC3 an
32、alog input 4 x tC4 analog input 5 x tCSee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B PAGE 7 TABLE I. Electrical perform
33、ance characteristics Continued. 1/ Test Symbol Conditions -55C TA +125C Limits Unit Min Max Timing section - continued Delay time, DATA-AV becomes active for the trigger level condition: TRIG0 = 0, TRG1 = 0 5/ td(DATA_AV)1 analog input, TL = 1 6 x tCns 2 analog inputs, TL = 2 7 x tC3 analog inputs,
34、TL = 3 8 x tC4 analog inputs, TL = 4 9 x tCDelay time, DATA-AV becomes active for the trigger level condition: TRIG0 = 1, TRG1 = 0 5/ td(DATA-AV) 1 analog input, TL = 4 3 x t2+ 6 x tC2 analog inputs, TL = 4 t2+7 x tC3 analog inputs, TL = 6 t2+ 8 x tC4 analog inputs, TL = 8 t2+ 9 x tCDelay time, DATA
35、-AV becomes active for the trigger level condition:TRIG0 = 0, TRG1 = 1 5/ td(DATA-AV)1 analog input, TL = 8 7 x t2+ 6 x tC2 analog inputs, TL = 8 3 x t2+ 7 x tC3 analog inputs, TL = 9 2 x t2+ 8 x tC4 analog inputs, TL = 12 2 x t2+ 9 x tCDelay time, DATA-AV becomes active for the trigger level condit
36、ion: TRIG0 = 1, TRG1 = 1 5/ td(DATA-AV)1 analog input, TL = 14 13 x t2+ 6 x tC2 analog inputs, TL = 12 5 x t2+ 7 x tC3 analog inputs, TL = 12 3 x t2+ 8 x tC1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified tempera
37、ture range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This test is not production tested. 3/ fS= 6 MHz,
38、f1= 2 MHz at 1 dBFS, AVDD= 5 V, BVDD= DVDD= 3.3 V, CL 30 pF. 4/ The SNR (ENOB) and SINAD is degraded typically be 2 dB in single-ended mode when the reading of data is asynchronous to the sampling clock. 5/ This timing parameter is ensured by design but is not tested. Provided by IHSNot for ResaleNo
39、 reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B PAGE 8 Case outline X Terminal Millimeters symbol Min Max A - 1.20 A1 - 0.25 b 0.19 0.30 C 0.15 - D 10.90 11.10 e - 0.65 E 6.20 - E1 7
40、.80 8.40 L 0.50 0.75 Q 0.05 0.15 N 32 NOTE: All dimensions are in millimeters. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B
41、 PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 D0 17 DGND 2 D1 18 DVDD3 D2 19 RD 4 D3 20 WR (R / W ) 5 D4 21 CS1 6 D5 22 CS0 7 BVDD23 AVDD8 BGND 24 AGND 9 D6 25 REFM 10 D7 26 REFP 11 D8 27 REFOUT 12 D9 28 REFIN 13 D10 / RA0 29 BINM 14 D11 / RA
42、1 30 BINP 15 CONV_CLK ( CONVST ) 31 AINM 16 DATA_AV 32 AINP FIGURE 2. Terminal connection. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03609 REV B PAGE 10 Term
43、inal symbol I / O Description AINP I Analog input, single-ended or positive input of differential channel A AINM I Analog input, single-ended or negative input of differential channel A BINP I Analog input, single-ended or positive input of differential channel B BINM I Analog input, single-ended or
44、 negative input of differential channel B AVDDI Analog supply voltage AGND I Analog ground BVDDI Digital supply voltage for buffer BGND I Digital ground for buffer CONV_CLK ( CONVST ) I Digital input. This input is used to apply an external conversion clock in continuous conversion mode. In single c
45、onversion mode, this input functions as the conversion start (CONVST ) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs. CS0 I Chip select input (active low) CS1 I Chip select input (
46、active high) DATA_AV O Data available signal, which can be used to generate an interrupt for processors and as level information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. DGND I Digital ground. Ground referen
47、ce for digital circuitry. DVDDI Digital supply voltage. D0-D9 I / O / Z Digital input, output; D0 = LSB D10/RA0 I / O / Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to the control register 0 and control regist
48、er 1. D11/RA1 I / O / Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. REFIN I Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REF
