1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate to current revision. - CFS 07-09-12 Thomas M. Hess B Add device type -02. - CFS 08-07-15 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV B B B B B B B B B B B B B B B B REV STATUS OF PAGES
2、PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thomas M. Hess APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, CMOS, THREE-PORT CABLE TRANSCEIVER/ARBITER, MONOLITH
3、IC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03612 YY-MM-DD 02-12-12 REV B PAGE 1 OF 16 AMSC N/A 5962-V052-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V6
4、2/03612 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Three-Port Cable Transceiver/Arbiter microcircuit, with an operating temperature range of -40C to +85C for device type 01, and an operating temperature range of -55C to +125C for device typ
5、e 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03612 - 01 X E Drawing Device type Case outline Lead f
6、inish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TSB41AB3-EP Three-Port Cable Transceiver/Arbiter 02 TSB41AB3-EP Three-Port Cable Transceiver/Arbiter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Numbe
7、r of pins JEDEC PUB 95 Package style X 80 JEDEC MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash
8、 palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) . -0.3 V to +4.0
9、V 2/ Input voltage range (VI). -0.5 V to VDD+ 0.5 V 2/ 5 V tolerant I/O supply voltage range (VDD(5V) -0.3 V to +5.5 V 5 V tolerant input voltage range (VI(5V) . -0.5 V to VDD(5V)+ 0.5 V Output voltage range at any output (VO) . -0.5 V to VDD+ 0.5 V Continuous total power dissipation: 3/ TA +25C. 5.
10、05 W TA= +70C. 2.69 W TA= +85C. 1.90 W Operating free-air temperature range (TA): Device type 01. -40C to +85C Device type 02. -55C to +125C Storage temperature range (TSTG). -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260C 1/ Stresses beyond those listed under “absolu
11、te maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extend
12、ed periods may affect device reliability. 2/ All voltage values, except differential I/O bus voltages, are with respect to network ground. 3/ Dissipation values are with a 2 oz. trace and copper pad with solder. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro
13、m IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 4 1.4 Recommended operating conditions. 1/ Supply voltage range (VDD) Source power node +3.0 V to +3.6 V Non-source power node +3.0 V to +3.6 V 2/ Minimum high level input voltage (VIH):
14、 Case 1 (bus holder): ISO = VDD, VDD(5V)= VDDCase 2 (5 V Tolerant): ISO = VDD, VDD(5V)= 5 V LREQ, CTL0, CTL1, D0-D7. +2.6 V C/LKON, PC0, PC1, PC2, ISO, PD . 0.7xVDDRESET 0.6xVDDMaximum low level input voltage (VIL): Case 1 (bus holder): ISO = VDD, VDD(5V)= VDDCase 2 (5 V Tolerant): ISO = VDD, VDD(5V
15、)= 5 V LREQ, CTL0, CTL1, D0-D7. +1.2 V C/LKON, PC0, PC1, PC2, ISO, PD . 0.2xVDDRESET 0.3xVDDOutput current (IO) (TPBIAS outputs) -5.6 mA to +1.3 mA Operating free-air temperature range (TA): Device type 01. -40C to +85C Device type 02. -55C to +125C Differential input voltage range (VID): Cable inpu
16、ts, during data reception . 118 mV to 260 mV Cable inputs, during arbitration 168 mV to 265 mV Common-mode input voltage (VIC): TPB cable inputs, source power node . 0.4706 V to 2.515 V TPB cable inputs, non-source power node 0.4706 V to 2.015 V 2/ Minimum power-up reset time (t(pu) (RESET input) 2
17、ms Maximum receive input jitter: TPA, TPB cable inputs, S100 operation 1.08 ns TPA, TPB cable inputs, S200 operation 0.5 ns TPA, TPB cable inputs, S400 operation 0.315 ns Maximum receive input skew: Between TPA and TPB cable inputs, S100 operation 0.8 ns Between TPA and TPB cable inputs, S200 operat
18、ion 0.55 ns Between TPA and TPB cable inputs, S400 operation 0.5 ns 1/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 2/ F
19、or a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 5 2. APPLICABLE DOCU
20、MENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) IEEE 1394-1995 - (1394) Standard for High-Performance
21、Serial Bus IEEE 1394a-2000 - (1394) Standard for High-Performance Serial Bus Supplement (Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08855-1331) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly
22、 marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if appli
23、cable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as speci
24、fied herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagram. The block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3.5.4 Timing waveforms and test circuit.
25、The timing waveforms and test circuit shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 6 TABLE I. Electrical perform
26、ance characteristics. 1/ Limits Test Symbol Test conditions unless otherwise specified VDD Temperature, TADevice type Min Max Unit 2/ 115 TYP 3/ 97 TSupply current IDD4/ 3.3 V 25C 75 TYP mA Supply current ultralow power mode IDD(ULP)Ports disabled, PD = 0 V, LPS = 0 V 3.3 V 25C 150 TYP A Power statu
27、s threshold, CPS input V(TH)5/ 400 k resistor 3.0 V and 3.6 V 4.7 7.5 V 2.7 V 2.2 High level output voltage VOHIOH= -4 mA For CTL0, CTL1, D0-D7, CNA, C/LKON, SYSCLK outputs. 3.0 V and 3.6 V 2.8 V Low level output voltage VOLIOL= 4 mA For CTL0, CTL1, D0-D7, CNA, C/LKON, SYSCLK outputs. 3.0 V and 3.6
28、V 0.4 V High level Annex J output voltage VOH(AJ)Annex J: IOH= -9 mA ISO = 0 V, VDD(5V)= VDDFor CTL0, CTL1, D0-D7, C/LKON, SYSCLK outputs. 3.0 V and 3.6 V VDD 0.4 V Low level Annex J output voltage VOL(AJ)Annex J: IOL= 9 mA ISO = 0 V, VDD(5V)= VDDFor CTL0, CTL1, D0-D7, C/LKON, SYSCLK outputs. 3.0 V
29、and 3.6 V 0.4 V Positive peak bus holder current I(BH+)ISO = 3.6 V VI= 0 V to VDD, VDD(5V)= VDDFor CTL0, CTL1, D0-D7, LREQ. 3.6 V 0.05 1 mA Negative peak bus holder current I(BH-)ISO = 3.6 V VI= 0 V to VDD, VDD(5V)= VDDFor CTL0, CTL1, D0-D7, LREQ. 3.6 V -1 -0.05 mA Input current IIISO = 0 V For LREQ
30、, LPS, PD, TESTM, SM, SE, PCO-PC2 inputs. 3.6 V Device type 01: -40C to +85C, Device type 02: -55C to +125C All 1 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A C
31、ODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test conditions unless otherwise specified VDD Temperature, TADevice type Min Max Unit Off-state output current IOZVO= VDDor 0 V For CTL0, CTL1, D0-D7, C/LKON I/Os. A
32、ll 5 A 01 -90 -20 Pullup current, RESET input I(RST)VI= 1.5 V or 0 V 02 -110 -20 A ISO = 0 V, VDD(5V)= VDDFor LREQ, CTL0, CTL1, D0-D7 inputs. 6/ VDD/2 + 0.3 VDD/2 + 0.9 Positive input threshold voltage VIT+ISO = 0 V, VDD(5V)= VDDVref= VDDx 0.4 For LPS inputs. Vref+ 1 V ISO = 0 V, VDD(5V)= VDDFor LRE
33、Q, CTL0, CTL1, D0-D7 inputs. 6/ VDD/2 - 0.9 VDD/2 - 0.3 Negative input threshold voltage VIT-ISO = 0 V, VDD(5V)= VDDVref= VDDx 0.4 For LPS inputs. Vref+ 0.2 V Output voltage, TPBIAS VOAt rated IOcurrent. 3.0 V and 3.6 V Device type 01: -40C to +85C, Device type 02: -55C to +125C All 1.665 2.015 V Dr
34、iver Differential output voltage VODRL= 56 See figure 4. 172 265 mV Driver difference current I(DIFF)Drivers enabled, speed signaling off For TPA+, TPA-, TPB+, TPB-. -1.05 7/ 1.05 7/ mA I(SP200)S200 speed signaling enabled For TPB+, TPB-. -4.84 8/ -2.53 8/ mA Common-mode speed signaling current I(SP
35、400)S400 speed signaling enabled For TPB+, TPB-. -12.4 8/ -8.1 8/ mA Off state differential voltage VOFFDrivers disabled. See figure 4. 3.0 V and 3.6 V Device type 01: -40C to +85C, Device type 02: -55C to +125C All 20 mV See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or
36、 networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test conditions unless otherwise specified VDD Temperature,
37、TADevice type Min Max Unit Receiver 4 k Differential impedance zidDrivers disabled. 4 pF 20 k Common-mode impedance zicDrivers disabled. 24 pF Receiver input threshold voltage V(TH_R)Drivers disabled. -30 30 mV Cable bias detect threshold voltage V(TH_CB)Drivers disabled. For TPB+ and TPB- cable inp
38、uts 0.6 1 V Positive arbitration comparator threshold voltage V(TH+)Drivers disabled. 89 168 mV Negative arbitration comparator threshold voltage V(TH-)Drivers disabled. -168 -89 mV V(TH_SP200)TPBIAS-TPA common- mode voltage, drivers disabled. 49 131 mV Speed signal threshold V(TH_SP400)TPBIAS-TPA c
39、ommon- mode voltage, drivers disabled. 3.0 V and 3.6 V Device type 01: -40C to +85C, Device type 02: -55C to +125C All 314 396 mV Thermal Characteristics Junction-to-ambient thermal resistance RJA19.04 TYP C/W Junction-to-case thermal resistance RJC9/ 0.17 TYP C/W Junction-to-ambient thermal resista
40、nce RJA31.52 TYP C/W Junction-to-case thermal resistance RJC10/ 0.17 TYP C/W Junction-to-ambient thermal resistance RJA49.17 TYP C/W Junction-to-case thermal resistance RJC11/ 3.0 V and 3.6 V Device type 01: -40C to +85C, Device type 02: -55C to +125C All 3.11 TYP C/W See footnotes at end of table.
41、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test conditio
42、ns unless otherwise specified VDD Temperature, TADevice type Min Max Unit Switching Characteristics Jitter, transmit Between TPA and TPB. 0.15 ns Skew, transmit Between TPA and TPB. 0.1 ns TP differential rise time, transmit tr10% to 90% At 1394 connector. 0.5 1.2 ns TP differential fall time, trans
43、mit tf90% to 10% At 1394 connector. 0.5 1.2 ns Setup time, tsu50% to 50%, See figure 4. For CTL0, CTL1, D1-D7, LREQ to SYSCLK. 5 ns Hold time th50% to 50%, See figure 4. For CTL0, CTL1, D1-D7, LREQ after SYSCLK. 3.0 V and 3.6 V Device type 01: -40C to +85C, Device type 02: -55C to +125C 2 ns Delay t
44、ime td50% to 50%, See figure 4. For SYSCLK to CTL0, CTL1, D1-D7. 3.3 V +25C All 2 ns LPS Timing Parameters LPS low time TLPSLWhen pulsed. 12/ 0.09 2.6 s LPS high time TLPSHWhen pulsed. 12/ 0.021 2.6 s LPS duty cycle When pulsed. 13/ 20% 55% LPS reset time TLPS_RESETTime for PHY to recognize LPS deas
45、serted and reset the interface. 2.6 2.68 s LPS disable time, TLPS_DISABLETime for PHY to recognize LPS deasserted and disable the interface. 26.03 26.11 s Restore time TRESTORETime to permit optional isolation circuits to restore during an interface reset. 15 23 14/ s Time for SYSCLK to be activated
46、 from reassertion of LPS. PHY not in low-power state. 60 ns SYSCLK activation time TCLK_ACTIVATETime for SYSCLK to be activated from reassertion of LPS. PHY in low-power state. 3.0 V and 3.6 V Device type 01: -40C to +85C, Device type 02: -55C to +125C All 5.3 7.3 ms See footnotes on next sheet. Pro
47、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03612 REV B PAGE 10 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing and other quality contr
48、ol techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design.
