1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device 02. Add case outline Y. Update boilerplate to current revision. - CFS 07-02-22 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-06-04 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA
2、 LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER, COLUMBUS COLUMB
3、US, OHIO 43218-3990 Original date of drawing YY MM DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS, MONOLITHIC SILICON 03-01-09 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03614 REV B PAGE
4、1 OF 17 AMSC N/A 5962-V061-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirement
5、s of a high performance 12-bit analog-to-digital converter microcircuit, with an operating temperature range of -40C to +125C for device type 01, and an operating temperature range of -55C to +125C for device type 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is th
6、e item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03614 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Gener
7、ic Circuit function 01 TLC2543-EP 12 bit analog-to-digital converter with serial control and 11 analog inputs 02 TLC2543-EP 12 bit analog-to-digital converter with serial control and 11 analog inputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JE
8、DEC PUB 95 Package style X 20 MS-013 Plastic small-outline Y 20 MO-150 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Pallad
9、ium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VCC)
10、0.5 V dc to +6.5 V dc 2/ Input voltage range (VIN)(any input). -0.3 V dc to VCC+0.3 V dc Output voltage (VOUT) -0.3 V dc to VCC+0.3 V dc Positive reference voltage, (Vref+). VCC+0.1 V dc Negative reference voltage, (Vref-)-0.1 V dc Peak input current (IIN) (any input) 20 mA Peak total input current
11、 (IIN) (all inputs) 30 mA Operating free-air temperature range (TA): Device type 01 . -40C to +125C Device type 02 . -55C to +125C Storage temperature range (TSTG) -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . +260C Thermal resistance, junction-to-case (JC): Case X . 2
12、9.8C/W Case Y . 21.9C/W 1.4 Recommended operating conditions. 3/ Supply voltage (VCC) . 4.5 V dc to 5.5 V dc Positive reference voltage, (Vref+) . VCCnominal 3/ Negative reference voltage, (Vref-) 0.0 V nominal 3/ Differential reference voltage, Vref+- Vref-+2.5 V dc to VCC+0.1 V dc 3/ Analog input
13、voltage . 0.0 V to VCC3/ High-level control input voltage, VIH(VCC= 4.5 V to 5.5 V) . 2.0 V dc minimum Low-level control input voltage, VIL(VCC= 4.5 V to 5.5 V) 0.8 V dc maximum Clock frequency at I/O CLOCK 0.0 MHz to 4.1 MHz Setup time, Address bits at DATA INPUT before I/O CLOCK, tsu(A). 100 ns mi
14、nimum Hold time, address bits after I/O CLOCK, th(A)0.0 ns minimum Hold time, CS low after last I/O CLOCK, th(CS). 0.0 ns minimum Setup time, CS low before clocking in first address bit, tsu(CS). 1.425 s 4/ Pulse duration, I/O CLOCK high, twH(I/O) 120 ns minimum Pulse duration I/O CLOCK low, twL(I/O
15、)120 ns minimum Transition time, I/O CLOCK, high to low, tt(I/O)1 s maximum 5/ Transition time, DATA INPUT and CS , tt(CS). 10 s maximum Operating free-air temperature range (TA): Device type 01 . -40C to +125C Device type 02 . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum ra
16、ting” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods m
17、ay affect device reliability. 2/ All voltage values are with respect to ground terminal with REF- and GND wired together (unless otherwise noted). 3/ Anaolg input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert
18、as all zeros (0000000000). 4/ To minimize errors caused by noise at CS input, the internal circuitry waits for a setup time after CS before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. 5/ This is the time required
19、for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 s for remote data acquisition applications where the sensor and the A/D converter are placed sever
20、al feet away from the controlling microprocessor. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECH
21、NOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking.
22、Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part n
23、umber and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction
24、 and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4
25、 Block diagram. The block diagram shall be as shown in figure 4. 3.5.5 Load circuit. The load circuit shall be as shown in figure 5. 3.5.6 Timing waveforms and test circuit. The timing waveforms shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted witho
26、ut license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Device type Limits Unit Min Max High level output voltage VOHIOH= -1.6 mA, VCC= 4.5 V All 2.4
27、 V IOH= -20 A, VCC= 4.5 V to 5.5 V VCC 0.1 Low level output voltage VOLIOL= 1.6 mA, VCC= 4.5 V 0.4 V IOL= 20 A, VCC= 4.5 V to 5.5 V 0.1 High impedance off-stat output current IOZVO= VCC, CS at VCC2.5 A VO= 0, CS at VCC-2.5 High level input current IIHVI= VCC10 A Low level input current IILVI= 0 V -1
28、0 A Operating supply current ICCCS at 0 V 2.5 mA Power down current ICC(PD)For all digital inputs, 0 VI 0.5 V or VI VCC 0.5 V 25 A Selected channe leakage current Selected channel at VCC, unselected channel at 0 V 10 A Selected channel at 0 V, unselected channel at VCC-10 Maximum static analog refer
29、ence current into REF+ Vref+= VCC, Vref-= GND 2.5 A Input capacitance CIAnalog inputs 60 pF Control inputs 15 Linearity error ELSee figure 5. 3/ 1 LSB Differential linearity error EDSee figure 5. 1 LSB Offset error EOSee figure 5. 4/ 5/ 1.5 LSB Gain error EGSee figure 5. 4/ 5/ 1 LSB Total unadjusted
30、 error ET6/ 1.75 LSB Self test output code DATA INPUT = 1011, See figure 3 7/ 2048 TYP DATA INPUT = 1100, See figure 3 7/ 0 TYP DATA INPUT = 1101, See figure 3 7/ 4095 TYP Conversion time t(conv)See figure 6. 10 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or network
31、ing permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 6 TABLE I. Electrical performance characteristics continued. 1/ Test Symbol Conditions 2/Device type Limits Unit Min Max Total cycle time (access, sample
32、 and conversion) tCSee figure 6. 8/ All 10 + total I/O CLOCK periods + td(I/O EOC)s Channel acquisition Time (sample) tacqSee figure 6. 8/ 4 12 I/O CLOCK periods Valid time, DATA OUT remains valid after I/O CLOCK tvSee figure 6. 10 ns Delay time, I/O CLOCK to DATA OUT valid td(I/O DATA)See figure 6
33、 150 ns Delay time, last I/O CLOCK to EOC td (I/O EOC) See figure 6. 2.2 s Delay time, EOC to DATA OUT (MSB/LSB) td(EOC DATA)See figure 6. 100 ns Enable time, CS to DATA OUT (MSB/LSB driven) tPZH, tPZLSee figure 6. 1.3 s Disable time, CS to DATA OUT (high impedance) tPHZ, tPLZSee figure 6. 150 ns R
34、ise time, EOC tr(EOC)See figure 6. 50 ns Fall time, EOC tf(EOC)See figure 6. 50 ns Rise time, data bus tr(bus)See figure 6. 50 ns Fall time, data bus tf(bus)See figure 6. 50 ns Delay time, last I/O CLOCK to CS to abort conversion td(I/O-CS)9/ 5 s 1/ Testing and other quality control techniques are u
35、sed to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assur
36、ed by characterization and/or design. 2/ Device type 01operated at -40C to +125C and device type 02 operated at -55C to +125C ; VCC=Vref+= 4.5 V to 5.5 V and f(I/O CLOCK)= 4.1 MHz unless otherwise specified. 3/ Linearity error is the maximum deviation from the best straight line through the A/D tran
37、sfer characteristic. 4/ Analog input voltages greater than applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert as all zeros (0000000000). 5/ Gain error is the difference between the actual midstep value and the nominal midstep value in the tr
38、ansfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep at the offset point. 6/ Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 7/ TA= +25C. Bot
39、h the input address and the output codes and expressed in positive logic. 8/ I/O CLOCK period = 1/(I/O CLOCK frequency). See figure 6. 9/ Any transitions of CS are recognized as valid only if the levels is maintained for a setup time. CS must be taken low at 5 s of the tenth I/O CLOCK falling edge t
40、o ensure a conversion is aborted. Between 5 s and 10 s, the result is uncertain as to whether the conversion is aborted or the conversion results are valid. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHI
41、O SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 7 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A 0.104 2.65 E 0.293 0.299 7.45 7.59 A1 0.004 0.012 0.10 0.30 E1 0.400 0.419 10.15 10.65 b 0.014 0.020 0.35 0.51 e 0.050 1.27 c 0.010 NOM
42、 0.25 NOM L 0.016 0.050 0.40 1.27 D 0.500 0.510 12.70 12.95 NOTE: 1. All linear dimensions are in inches (millimeters). Millimeters equivalents are shown for reference only. 2. Body dimensions do not include mold flash or protrusion. 3. This drawing is subject to change without notice. 4. Falls with
43、in JEDEC MS-013 variation AC. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 8 Case Y SEATINGPLANESEEDETAIL AbD1011E E1A
44、1e.004(0.10)c0-8LDETAIL AGAGEPLANEM .010(0.25)120A.010(0.25)Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 2.00 - 0.079 E 5.00 5.60 0.197 0.220 A1 0.05 - 0.002 - E1 7.40 8.20 0.291 0.323 b 0.22 0.38 0.009 0.015 e 0.65 BSC 0.026 BSC c 0.09 0.25 0.00
45、4 0.010 L 0.55 0.95 0.022 0.037 D 6.90 7.50 0.272 0.295 NOTE: 1. All linear dimensions are in millimeters (inches). Inches equivalents are shown for reference only. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mill
46、imeters (0.006 inches). 4. Falls within JEDEC MO-150. FIGURE 1. Case outlines - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03614 REV B PAGE 9 Devic
47、e types 01 and 02 Case outlines X and Y Terminal number Terminal symbol 1 AIN0 2 AIN1 3 AIN2 4 AIN3 5 AIN4 6 AIN5 7 AIN6 8 AIN7 9 AIN8 10 GND 11 AIN9 12 AIN10 13 REF- 14 REF+ 15 CS 16 DATA OUT 17 DATA INPUT 18 I/O CLOCK 19 EOC 20 VCCPin description Terminal symbol Description AINn (n = 0 to 10) Anal
48、og signal inputs CS Chip select DATA INPUT Serial data input DATA OUT Serial data output EOC End of conversion GND Ground I/O CLOCK Input / Output clock REF+ Positive reference voltage REF- Negative reference voltage VCCPositive supply voltage FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or n
