1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add EP suffix to generic number and correct the vendor part number. - CFS 04-01-29 Thomas M. Hess B Correct lead finish. Update boilerplate. - CFS 05-11-08 Thomas M. Hess C Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess C
2、URRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV C C C C PAGE 40 41 42 43 REV C C C C C C C C C C C C C C C C C C C C C C PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 3
3、4 35 36 37 38 39 REV STATUS OF PAGES REV C C C C C C C C C C C C C C C C C PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED
4、POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON YY MM DD 03-12-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04605 REV C PAGE 1 OF 43 AMSC N/A 5962-V043-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN
5、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04605 REV C PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Dr
6、awing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04605 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1)
7、 (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 SM32VC5510-EP Fixed Point Digital Signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 240 Plastic ball grid array 1.2.3 Lead finishes
8、. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 2/ Supply voltage I/O range, (DVDD) . -0.3 V to +4
9、.0 V 3/ Supply voltage core range, (CVDD) . -0.3 V to +2.0 V 3/ Input voltage range, (VI) . -0.3 V to +4.5 V Output voltage range, (VO) . -0.3 V to +4.5 V Operating case temperature ranges, (TC): (Extended) . -40C to +85C 4/ Storage temperature range, (TSTG) -55C to +150C 4/ 1/ Users are cautioned t
10、o review the manufacturers data manual for additional user information relating to this device. 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other condit
11、ions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS. 4/ Long term high temperature storage and/or extended use at maximum r
12、ecommended operating conditions may result in a reduction of overall device life. See manufacturer data for additional information on enhanced plastic packaging. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS
13、, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04605 REV C PAGE 3 1.4 Recommended operating conditions. 3/ Device supply voltage, I/O (DVDD) +3.0 V to +3.6 V Device supply voltage, core (CVDD) +1.55 V to +1.65 V 5/ Supply voltage, GND (VSS) . 0 V High level input voltage, I/O (VIH): Hysteresis input
14、s, DVDD= 3.3 0.3 V 2.4 V to DVDD+ 0.3 V All other inputs 2.0 V to DVDD+ 0.3 V Low level input voltage, I/O (VIL): Hysteresis inputs, DVDD= 3.3 0.3 V -0.3 V to +0.8 V All other inputs -0.3 V to +0.8 V High level output current, (IOH), All outputs: -8 mA maximum Low level output current, (IOL), All ou
15、tputs: . 8 mA maximum Operating case temperature (TC), Extended temperature range -40C to +85C Junction to case (RJC) Board type: 2s JEDEC test card 5/ . 6C/W Junction to air (RJA) Board type: High K 6/ Air flow = 0 LFM 26C/W Air flow = 150 LFM 22C/W Air flow = 250 LFM 20C/W Board type: Low K 6/ Air
16、 flow = 0 LFM 50C/W Air flow = 150 LFM 35C/W Air flow = 250 LFM 29C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-9 Test Boards for Area Array Surface Mount Package Thermal Measurements. (Copies of t
17、hese documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 5/ Prototype revision 2.1 and 2.2 and production silicon. See the TMS320VC5510 Digital Signal Silicon Errata (literature number SPRZ0
18、08) for further clarification and distinguishing marking. 6/ Board types are as defined by JEDEC. See JEDEC Standard JESD51-9. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236
19、DWG NO. V62/04605 REV C PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The
20、unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, co
21、nstruction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 L
22、oad circuit. The load circuit shall be as specified in figure 4. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figures 5 - 27. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A C
23、ODE IDENT NO. 16236 DWG NO. V62/04605 REV C PAGE 5 TABLE I. Electrical performance characteristics. 1/ No. Test Symbol Test condition -40C TC+85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max High level output voltage All output except CLKOUT VOHDVDD= 3.3 0.3 V, IOH=
24、 Max 2.4 V CLKOUT CVDD= 1.6 0.05 V, IOH= Max 1.24 Low level output voltage VOLIOL= Max 0.4 V Input current for outputs in high impedance Output only or input/output pins with bus holders IIZBus holders enabled CVDD= Max, VO= VSSto VDD-275 275 A All other output only or input/output pins Bus holders
25、disabled CVDD= Max, VO= VSSto VDD-5 5 Input current Input pins with internal pulldown IICVDD= Max, VI= VSSto VDD-5 300 A Input pins with internal pullup Pullup enabled CVDD= Max, VI= VSSto VDD-300 5 All other input only pins or input only pins with pullup/plldown disabled CVDD= Max, VI= VSSto VDD-5
26、5 CVDDsupply current, CPU plus internal memory access 2/ IDDCCVDD= 1.6 V, TC= 25C CPU clock = 200 MHz 112 Typ mA DVDD supply current, pins active 3/ IDDPDVDD= 3.3 V, TC= 25C CPU clock = 100 MHz 8 Typ mA CVDDsupply current, standby Only CLKGEN domain enabled, PLL enabled IDDCCVDD= 1.6 V, TC= 25C 10 M
27、Hz clock input, DLL mode = x 20 32 Typ mA CVDDsupply current, standby All domains idled IDDCCVDD= 1.6 V, TC= 25C Input clock stopped. 69 Typ A CVDD= 1.6 V, TC= 55C Input clock stopped. 374 Typ CVDD= 1.6 V, TC= 85C Input clock stopped. 976 Typ DVDD supply current, standby All domains idled IDDPDVDD=
28、3.3 V, TC= 25C No pin activity. 10 Typ A DVDD= 3.3 V, TC= 55C No pin activity. 10 Typ DVDD= 3.3 V, TC= 85C No pin activity. 10 Typ Input capacitance CI3 Typ pF Output capacitance CO3 Typ pF See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without licens
29、e from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04605 REV C PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition -40C TC+85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit M
30、in Max CLOCK GENERATION IN BYPASS MODE (DPLL Disabled) CLKIN in Bypass Mode Timing Requirements C7 Cycle time, CLKIN tc(CI)See figure 5 20 4/ ns C8 Fall time, CLKIN tf(CI)6 C9 Rise time, CLKIN tr(CI)C10 Pulse duration, CLKIN low tW(CIL)4 C11 Pulse duration, CLKIN high tW(CIH)CLKOUT in bypass mode sw
31、itching characteristics C1 Cycle time, CLKOUT 5/ tc(CO)See figure 5 20 ns C2 Delay time, CLKIN high/low to CLKOUT high/low td(CI-CO)1 14C3 Fall time, CLKOUT tf(CO)TypC4 Rise time, CLKOUT tr(CO)TypC5 Pulse duration , CLKOUT low tW(COL)H-1 H+1 C6 Pulse duration , CLKOUT high tW(COH)H-1 H+1 CLOCK GENER
32、ATION IN LOCK MODE (DPLL Synthesis Enabled) CLKIN in lock mode timing requirements C7 Cycle time, CLKIN DPLL synthesis enable tc(CI)See figure 6 20 6/ 400 ns C8 Fall time, CLKIN tf(CI)6 C9 Rise time, CLKIN tr(CI)C10 Pulse duration, CLKIN low tW(CIL)4 C11 Pulse duration, CLKIN high tW(CIH)CLKOUT in l
33、ock mode switching characteristics C1 Cycle time, CLKOUT tc(CO)See figure 6 5 ns C2 Delay time, CLKIN high/low to CLKOUT high/low td(CI-CO)1 14C3 Fall time, CLKOUT tf(CO)TypC4 Rise time, CLKOUT tr(CO)TypC5 Pulse duration , CLKOUT low tW(COL)H-1 H+1 C6 Pulse duration , CLKOUT high tW(COH)H-1 H+1 See
34、notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04605 REV C PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test
35、Symbol Test condition -40C TC+85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max ASYNCHRONOUS MEMORY TIMING Asynchronous memory cycles timing requirements A6 Setup time, read data valid before CLKOUT high 7/ tsu(DV-COH)See figure 7 and 8 6 ns A7 Hold time, read data v
36、alid after CLKOUT high th(COH-DV)0 A10 Setup time, ARDY valid before CLKOUT high tsu(ARDY-COH)7 A11 Hold time, ARDY valid after CLKOUT high th(COH-ARDY)Asynchronous memory cycle switching characteristics 8/ 9/ A1 Delay time, CLKOUT high to CEx transaction td(COH-CEV)See figure 7 and 8 -2 4 ns A2 Del
37、ay time, CLKOUT high to BEx valid td(COH-BEV)A3 Delay time, CLKOUT high to BEx invalid td(COH-BEIV)-2 A4 Delay time, CLKOUT high to address valid td(COH-AV)4 A5 Delay time, CLKOUT high to address invalid td(COH-AIV)-2 A8 Delay time, CLKOUT high to AOE valid td(COH-AOEV)4 A9 Delay time, CLKOUT high t
38、o ARE td(COH-AREV)-2 A12 Delay time, CLKOUT high to data valid (write) td(COH-DV)4 A13 Delay time, CLKOUT high to data invalid (write) td(COH-DIV)-2 A14 Delay time, CLKOUT high to AWE valid td(COH-AWEV)4 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted
39、without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04605 REV C PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition -40C TC+85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted
40、 Limits Unit Min Max SYNCHRONOUS BURST SRAM (SBSRAM) TIMING Synchronous burst SRAM cycle timing requirements SB7 Setup time, read data valid before CLKMEM high tsu(DV-CLKMEMH)See figure 9 5 ns SB8 Hold time, read data valid after CLKMEM high th(CLKMEMH-DV)2 Synchronous burst SRAM cycle switching cha
41、racteristics SB1 Delay time, CLKMEM high to CEx low td(CLKMEMH-CEL)See figure 9 3 6 ns SB2 Delay time, CLKMEM high to CEx high td(CLKMEMH-CEH)3 SB3 Delay time, CLKMEM high to BEx valid td(CLKMEMH-BEV)6 SB4 Delay time, CLKMEM high to BEx invalid td(CLKMEMH-BEIV)3 6 SB5 Delay time, CLKMEM high to addr
42、ess valid td(CLKMEMH-AV)SB6 Delay time, CLKMEM high to address invalid td(CLKMEMH-AIV)3 6 SB9 Delay time, CLKMEM high to SSADS low td(CLKMEMH-ADSL)SB10 Delay time, CLKMEM high to SSADS high td(CLKMEMH-ADSH)3 6 SB11 Delay time, CLKMEM high to SSOE low td(CLKMEMH-OEL)6 SB12 Delay time, CLKMEM high to
43、SSOE high td(CLKMEMH-OEH)3 6 SB13 Delay time, CLKMEM high to data valid td(CLKMEMH-DV)6 SB14 Delay time, CLKMEM high to data invalid td(CLKMEMH-DIV)3 SB15 Delay time, CLKMEM high to SSWE low td(CLKMEMH-WEL)6 SB16 Delay time, CLKMEM high to SSWE high td(CLKMEMH-WEH)3 6 See notes at end of table. Prov
44、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04605 REV C PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition -40C
45、TC+85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max SYNCHRONOUS DRAM (SDRAM) TIMING Synchronous DRAM cycle timing requirements SB7 Setup time, read data valid before CLKMEM high tsu(DV-CLKMEMH)See figure 10-12 5 ns SB8 Hold time, read data valid after CLKMEM high th
46、(CLKMEMH-DV)2 Synchronous DRAM cycle switching characteristics SB1 Delay time, CLKMEM high to CEx low td(CLKMEMH-CEL)See figure 10-12 3 6 ns SB2 Delay time, CLKMEM high to CEx high td(CLKMEMH-CEH)3 SB3 Delay time, CLKMEM high to BEx valid td(CLKMEMH-BEV)6 SB4 Delay time, CLKMEM high to BEx invalid t
47、d(CLKMEMH-BEIV)3 SB5 Delay time, CLKMEM high to address valid td(CLKMEMH-AV)6 SB6 Delay time, CLKMEM high to address invalid td(CLKMEMH-AIV)3 SB9 Delay time, CLKMEM high to SDCAS low td(CLKMEMH-SDCASL)5 SB10 Delay time, CLKMEM high to SDCAS high td(CLKMEMH-SDCASH)3 5 SB11 Delay time, CLKMEM high to
48、data valid td(CLKMEMH-DV)5 SB12 Delay time, CLKMEM high to data invalid td(CLKMEMH-DIV)3 SB13 Delay time, CLKMEM high to SDWE low td(CLKMEMH-SDWEL)5 SB14 Delay time, CLKMEM high to SDWE high td(CLKMEMH-SDWEH)3 5 SB15 Delay time, CLKMEM high to SDA10 valid td(CLKMEMH-SDA10V)5 SB16 Delay time, CLKMEM high to SDA10 invalid td(CLKMEMH-SDA10IV)3 SB17 Delay time, CLKMEM high to SSWE low td(CLKME
