1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-06-22 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charl
2、es F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-03-11 AP
3、PROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04675 REV A PAGE 1 OF 10 AMSC N/A 5962-V059-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/0
4、4675 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT octal transparent D-type latch with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manu
5、facturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04675 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s)
6、. Device type Generic Circuit function 01 SN74LVTH373-EP 3.3-V ABT octal transparent D-type latch with 3-state outputs 1.2.2 Case outline. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MO-153 Plastic small-outline1.2.3 Lead finishes. The lead
7、 finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
8、IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04675 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or pow
9、er-off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state (VO) . -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state (IO) . 64 mA 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK
10、) (VO 0) . -50 mA Package thermal impedance (JA) . 83C/W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high level input voltage (VIH) 2.0 V Maximum low level input voltage (VIL) . 0.8 V Maximum input
11、 voltage (VI) . 5.5 V Maximum high level output current (IOH) . -32 mA Maximum low level output current (IOL) . 64 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA) -40C to +85C 1/ Stress
12、es beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolut
13、e-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the output is in the high state and VO VCC. 4/ The package therm
14、al impedance is calculated in accordance with JESD 51-7. 5/ All unused control inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distri
15、butor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04675 REV A PAGE 4 2. APPL
16、ICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arli
17、ngton, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional)
18、3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table
19、I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 L
20、ogic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproductio
21、n or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04675 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -40C TA 85C unless otherwise specified VCCLimits Unit Min Max In
22、put clamp voltage VIKII= -18 mA 2.7 V -1.2 V High level output voltage VOHIOH= -100 A 2.7 V to 3.6 V VCC 0.2 IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3.0 V 2.0 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 IOL= 24 mA 0.5 IOL= 16 mA 3.0 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIVI= 5.5 V 0 V or
23、 3.6 V 10 A Control inputs, VI= VCCor GND 3.6 V 1 Data inputs, VI= VCCData inputs, VI= 0 V -5 Input/output power-off leakage current IoffVIor VO= 0 to 4.5 V 0 V 100 A Input current (hold) II(hold)Data inputs, VI= 0.8 V 3 V 75 AData inputs, VI= 2 V -75 Data inputs, VI= 0 V to 3.6 V 3.6 V 2/ +500 -750
24、 3-state output current high IOZHVO= 3 V 3.6 V 5 A 3-state output current low IOZLVO= 0.5 V 3.6 V -5 A 3-state output current power-up IOZPUVO= 0.5 V to 3 V, OEnullnullnullnull= dont care 0 V to 1.5 V 100 A 3-state output current power-down IOZPDVO= 0.5 V to 3 V, OEnullnullnullnull= dont care 1.5 V
25、to 0 V 100 A Quiescent supply current ICCOutputs high VI= VCCor GND, IO= 0 A 3.6 V 0.19 mA Outputs low. VI= VCCor GND, IO= 0 A 5 Outputs disabled. VI= VCCor GND, IO= 0 A 0.19 Quiescent supply current delta ICC3/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance
26、CiVI= 3 V or 0 V, TA= 25C 3.3 V 3 TYP pF Output capacitance CoVO= 3 V or 0 V, TA= 25C 7 TYP See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG
27、NO. V62/04675 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions -40C TA 85C unless otherwise specified VCCLimits Unit Min Max Pulse duration, LE high twSee figure 5. 2.7 V 3 ns 3.3 V 0.3 V 3 Setup time, data before LE tsu 2.7 V 0.43.3 V 0.3 V 1.1 Hol
28、d time, data after LE th 1.43.3 V 0.3 V 1.4 Propagation delay time, D to Q tPLHCL= 50 pF See figure 5. 2.7 V 4.5 ns 3.3 V 0.3 V 1.5 3.9 tPHL2.7 V 4.53.3 V 0.3 V 1.5 3.9 Propagation delay time, LE to Q tPLH4.93.3 V 0.3 V 1.7 4.2 tPHL2.7 V 4.93.3 V 0.3 V 1.7 4.2 Propagation delay time, output enable,
29、OEnullnullnullnullto Q tPZH5.93.3 V 0.3 V 1.3 4.8 tPZL2.7 V 5.53.3 V 0.3 V 1.3 4.8 Propagation delay time, output disable, OEnullnullnullnullto Q tPHZ4.93.3 V 0.3 V 1.9 4.6 tPLZ2.7 V 4.63.3 V 0.3 V 1.9 4.5 1/ Testing and other quality control techniques are used to the extent deemed necessary to ass
30、ure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/
31、This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 3/ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCCor GND. Provided by IHSNot for ResaleNo reprod
32、uction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04675 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 E 4.30 4.50 0.1
33、69 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 BSC 0.026 BSC c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 6.40 6.60 0.252 0.260 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body
34、dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A
35、CODE IDENT NO. 16236 DWG NO. V62/04675 REV A PAGE 8 (each latch) Inputs Output OEnullnullnullnullLE D Q L H H H L H L L L L X Q0H X X Z H = High voltage level X = Immaterial L = Low voltage level Z = High-impedance state Q0= Level of Q before the indicated steady-state input conditions were establis
36、hed. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X Terminal number Terminal symbol Terminal number Terminal symbol 1 OEnullnullnullnull11 LE 2 1Q 12 5Q 3 1D 13 5D 4 2D 14 6D5 2Q 15 6Q 6 3Q 16 7Q 7 3D 17 7D 8 4D 18 8D9 4Q 19 8Q 10 GND 20 VCCFIGURE 4. Terminal connect
37、ions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04675 REV A PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with intern
38、al conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR
39、 10 MHz, ZO= 50 , tr 2.5 ns, and tf 2.5 ns. 4. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUM
40、BUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04675 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper h
41、andling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for
42、electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manuf
43、acturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of su
44、pply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04675-01XE 01295 SN74LVTH373IPWREP LH373EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering
45、 documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
