1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Correct vendor part number in 6.3. Updated boiler plate. - phn 04-06-16 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 10-12-08 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STA
2、TUS OF PAGES REV B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 8-BIT PARALLEL LOAD SHIFT REGISTER, MONOLI
3、THIC SILICON YY MM DD 04-04-26 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04689 REV B PAGE 1 OF 12 AMSC N/A 5962-V017-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT N
4、O. 16236 DWG NO. V62/04689 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 8-bit parallel load shift register microcircuit, with an operating temperature range of -40C to +125C for device type 01 and -55C to +125C for device type 02. 1.2 Vendor
5、Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04689 - 01 X E Drawing Device type Case outline Lead finish number (See
6、 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Operating temperature Circuit function 01 SN74HC165-EP -40C TA+125C 8-bit parallel load shift register. 02 SN74HC165-EP -55C TA+125C 8-bit parallel load shift register. 1.2.2 Case outline(s). The case outlines are as specified
7、 herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MS-012 Plastic small outline package Y 16 JEDEC MO-153 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish design
8、ator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VCC) . -0.5 V to +7.0 V Input clamp current, (IIK) (VIVCC) 20 mA 2/ Output clamp current, (IOK) (VOVCC) 20 mA 2/ Continuous output current, (IO
9、) (VO= 0 to VCC) . 25 mA Continuous current through VCCor GND 50 mA Package thermal impedance (JA): 3/ X package . 73C/W Y package . 108C/W Storage temperature range, (TSTG) -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These
10、are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output v
11、oltage ratings may exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A
12、 CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 3 1.4 Recommended operating conditions. 4/ 5/ Supply voltage, (VCC) +2.0 V to +6.0 V Minimum high level input voltage, (VIH): VCC= 2.0 V . +1.5 V VCC= 4.5 V . +3.15 V VCC= 6.0 V . +4.2 V Maximum low level input voltage, (VIL): VCC= 2.0 V . +0.5 V VC
13、C= 4.5 V . +1.35 V VCC= 6.0 V . +1.8 V Input voltage, (VI) 0.0 V to VCCOutput voltage, (VO) 0.0 V to VCCMaximum input transition rise/fall rate (t/v) 6/ VCC= 2.0 V . 1000 ns VCC= 4.5 V . 500 ns VCC= 6.0 V . 400 ns Operating free air temperature, (TA): Device type 01 -40C to +125C Device type 02 -55C
14、 to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking.
15、 Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part
16、number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, constructio
17、n, and physical dimensions are as specified herein. 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintai
18、n no responsibility or liability for product used beyond the stated limits. 6/ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt= 100
19、0 ns and VCC= 2 V does not damage the device; however, functionally the CLK inputs are not ensured while in the shift, count, or toggle operating modes. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE
20、IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 4 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3
21、.5.4 Function table. The function table shall be as shown in figure 4. 3.5.5 Sequence waveforms. The sequence waveforms shall be as shown in figure 5. 3.5.6 Load circuit and timing waveforms. The load circuit and timing waveforms shall be as specified in figure 6. Provided by IHSNot for ResaleNo rep
22、roduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTA= 25C All device types 2/ Unit Min Max Min Max High level out
23、put voltage VOHVI= VIHor VILIOH= -20 A 2.0 V 1.9 1.9 V 4.5 V 4.4 4.4 6.0 V 5.9 5.9 IOH= -4.0 mA 4.5 V 3.98 3.7 IOH= -5.2 mA 6.0 V 5.48 5.2 Low level output voltage VOLVI= VIHor VILIOL= 20 A 2.0 V 0.1 0.1 4.5 V 0.1 0.1 6.0 V 0.1 0.1 IOL= 4.0 mA 4.5 V 0.26 0.4 IOL= 5.2 mA 6.0 V 0.26 0.4 Input current
24、IIVI= VCCor 0 6.0 V 100 1000 nA Quiescent supply current ICCVI= VCCor 0, IO= 0 6.0 V 8 160 A Input capacitance CI2.0 V to 6.0 V 10 10 pF Timing requirements Clock frequency fclock2.0 V 6 4.2 MHz 4.5 V 31 21 6.0 V 36 25 Pulse duration twSH/ LD low 2.0 V 80 120 ns 4.5 V 16 24 6.0 V 14 20 CLK high or l
25、ow 2.0 V 80 120 4.5 V 16 24 6.0 V 14 20 Setup time tsuSH/ LD high before CLK 2.0 V 80 120 4.5 V 16 24 6.0 V 14 20 SER before CLK 2.0 V 40 60 4.5 V 8 12 6.0 V 7 10 CLK INH low before CLK 2.0 V 100 150 4.5 V 20 30 6.0 V 17 25 CLK INH high before CLK 2.0 V 40 60 4.5 V 8 12 6.0 V 7 10 Data before SH/ LD
26、 2.0 V 100 150 4.5 V 20 30 6.0 V 17 26 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 6 TABLE I. Electrical performance chara
27、cteristics - Continued. 1/ Test Symbol ConditionsVCCTA= 25C All device types 2/ Unit Min Max Min Max Timing requirements - Continued Hold time thSER data after CLK 2.0 V 5 5 ns 4.5 V 5 5 6.0 V 5 5 PAR data after SH/ LD 2.0 V 5 5 4.5 V 5 5 6.0 V 5 5 Switching characteristics Maximum frequency fmax2.0
28、 V 6 4.2 MHz 4.5 V 31 21 6.0 V 36 25 From input SH/ LD to output QHor QHtpd2.0 V 150 225 ns 4.5 V 30 45 6.0 V 26 38 From input CLK to output QHor QH2.0 V 150 225 4.5 V 30 45 6.0 V 26 38 From input H to output QHor QH2.0 V 150 225 4.5 V 30 45 6.0 V 26 38 Transition time from any input to output tt2.0
29、 V 75 1104.5 V 15 22 6.0 V 13 19 Power dissipation capacitance CpdNo load 2.0 V 75 Typ pF 1. Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full
30、temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2. -40C TA+125C for device type 01. -55C TA+125C for device type 02. Provided by IHSNot for ResaleNo reproduction or ne
31、tworking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 7 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A - 0.069 - 1.75 E 0.150 0.157 3.81 4.00 A1 0.004 0.01
32、0 0.10 0.25 E1 0.228 0.244 5.80 6.20 b 0.014 0.020 0.35 0.51 e 0.050 BSC 1.27 BSC c 0.008 NOM 0.20 NOM L 0.016 0.044 0.40 1.12 D 0.386 0.394 9.80 10.00 Notes: 1. All linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Body dimensions do not include
33、mold flash or protrusion, not to exceed 0.006 (0.15). 4. Fall within JEDEC MS-012 FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 8
34、 Case Y Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A - 0.047 - 1.20 E 0.169 0.177 4.30 4.50 A1 0.002 0.006 0.05 0.15 E1 0.244 0.260 6.20 6.60 b 0.007 0.012 0.19 0.30 e 0.026 BSC 0.65 BSC c 0.006 NOM 0.15 NOM L 0.020 0.75 0.50 0.75 D 0.193 0.200 4.9
35、0 5.10 Notes: 1. All linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0.15). 4. Fall within JEDEC MO-153 FIGURE 1. Case outlines - Continued. Provided by IHSNot for Res
36、aleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 9 Case X or Y Pin No. Signal name Pin No. Signal name 1 SH/ LD 9 QH2 CLK 10 SER 3 E 11 A 4 F 12 B 5 G 13 C 6 H 14 D 7 QH15 CLK INH 8 G
37、ND 16 VCCFIGURE 2. Terminal connections. FIGURE 3. Logic diagram. Inputs Function SH/ LD CLK CLK INH L X X Parallel load H H X No changeH X H No change H L Shift 1/ H L Shift 1/ 1. Shift = content of each internal register shifts toward serial output QH. Data at SER is shifted into the first registe
38、r FIGURE 4. Function Table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 10 FIGURE 5. Sequence waveforms. Provided by IHSNot for ResaleNo reproduction or
39、networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 11 Notes: 1. CLincludes probe and test fixture capacitance. 2. Phase relationships between waveforms were chosen arbitrarily. All input pulse are supplied b
40、y generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr= 6 ns, tf= 6 ns. 3. For clock inputs, fmaxis measured when the input duty cycle is 50%. 4. The outputs are measured one at a time with one input transition per measurement. 5. tPLHand tPHLare the same tpd. FIGURE 6. Load circu
41、it and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04689 REV B PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsi
42、ble for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5
43、.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Con
44、figuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identifica
45、tion of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04689-01XE 01295
46、SN74HC165QDREP HC165EPV62/04689-01YE 01295 SN74HC165QPWREP HC165EP V62/04689-02YE 01295 2/ HC165MEP1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ Not yet available from a source of supply. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
