1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-12-08 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY RICK
2、OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL, TRIPLE 3-INPUT POSITIVE AND GATE, MONOLITHIC SILICON 04-04-19 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04692 RE
3、V A PAGE 1 OF 13 AMSC N/A 5962-V019-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirement
4、s of a high performance triple 3-input positive AND gate microcircuit, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control numbe
5、r for identifying the item on the engineering documentation: V62/04692 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LV11A-EP Triple 3-input positive AND gate 1.2.2 Case outline(s). T
6、he case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MO-153 Plastic small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip
7、 B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Su
8、pply voltage range ( VCC) -0.5 V to 7 V Input voltage range ( VI) -0.5 V to 7 V 2/ Output voltage range applied in high or low state ( VO) -0.5 V to VCC+0.5 V 2/ 3/ Voltage range applied to any output in the power off state ( VO) -0.5 V to 7 V 2/ Input clamp current ( IIK) ( VI 0 ) -20 mA Output cla
9、mp current ( IOK) ( VO 0 or VO VCC) . 50 mA Continuous output current ( IO) ( VO= 0 to VCC) . 25 mA Continuous current through VCCor GND . 50 mA Package thermal impedance ( JA) . 113C/W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ 6/ Supply voltage rang
10、e ( VCC) 2 V minimum to 5.5 V maximum High level input voltage ( VIH): VCC= 2 V . 1.5 V minimum VCC= 2.3 V to 2.7 V VCCx 0.7 V minimum VCC= 3 V to 3.6 V . VCCx 0.7 V minimum VCC= 4.5 V to 5.5 V VCCx 0.7 V minimum Low level input voltage ( VIL): VCC= 2 V . 0.5 V maximum VCC= 2.3 V to 2.7 V VCCx 0.3 V
11、 maximum VCC= 3 V to 3.6 V . VCCx 0.3 V maximum VCC= 4.5 V to 5.5 V VCCx 0.3 V maximum Input voltage ( VI) 0 V minimum to 5.5 V maximum Output voltage ( VO) 0 V minimum to VCCmaximum High level output current ( IOH): VCC= 2 V . -50 A maximum VCC= 2.3 V to 2.7 V -2 mA maximum VCC= 3 V to 3.6 V . -6 m
12、A maximum VCC= 4.5 V to 5.5 V -12 mA maximum 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended ope
13、rating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ This value is limited to 5.5 V maximum. 4/ The package
14、 thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distribu
15、tor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 4 1.4 Recommended ope
16、rating conditions - continued. 5/ 6/ Low level output current ( IOL): VCC= 2 V . 50 A maximum VCC= 2.3 V to 2.7 V 2 mA maximum VCC= 3 V to 3.6 V . 6 mA maximum VCC= 4.5 V to 5.5 V 12 mA maximum Input transition rise or fall rate ( t / v ): VCC= 2.3 V to 2.7 V 200 ns / V maximum VCC= 3 V to 3.6 V . 1
17、00 ns / V maximum VCC= 4.5 V to 5.5 V 20 ns / V maximum Operating free-air temperature range ( TA) -40C to +105C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Pa
18、ckages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 h
19、erein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum an
20、d recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outl
21、ine shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Timing waveforms and test cir
22、cuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 5 TABLE I. Electrical performance
23、 characteristics. 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Electrical characteristics section. High level output voltage VOHIOH= -50 A, VCC= 2 V to 5.5 V -40C to 105C 01 VCC 0.1 V IOH= -2 mA, VCC= 2.3 V 2 IOH= -6 mA, VCC= 3 V 2.48 IOH= -12 mA, VCC= 4.5 V 3.8 Low level
24、output voltage VOLIOL= 50 A, VCC= 2 V to 5.5 V -40C to 105C 01 0.1 V IOL= 2 mA, VCC= 2.3 V 0.4 IOL= 6 mA, VCC= 3 V 0.44 IOL= 12 mA, VCC= 4.5 V 0.55 Input current IIVI= 5.5 V or GND, VCC= 0 to 5.5 V -40C to 105C 01 1 A Supply current ICCVI= VCCor GND, IO= 0, VCC= 5.5 V -40C to 105C 01 20 A Off curren
25、t IoffVIor VO= 0 to 5.5 V, VCC= 0 -40C to 105C 01 5 A Input capacitance CiVI= VCCor GND, VCC= 3.3 V -40C to 105C 01 1.9 typical pF Switching characteristics section. See figure 5 Power dissipation time tpdFrom input A, B, or C, To output Y, +25C 01 17.5 ns VCC= 2.5 V 0.2 V, CL= 50 pF -40C to 105C 1
26、21 From input A, B, or C, To output Y, +25C 12.3 VCC= 3.3 V 0.3 V, CL= 50 pF -40C to 105C 1 14 From input A, B, or C, To output Y, +25C 7.9 VCC= 5 V 0.5 V, CL= 50 pF -40C to 105C 1 9 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f
27、rom IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 6 TABLE I. Electrical performance characteristics continued. 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Noise characteristics section. 2/ Quiet output, maximum dynam
28、ic VOLVOL(P)VCC= 3.3 V, CL= 50 pF +25C 01 0.8 V Quiet output, minimum dynamic VOLVOL(V)VCC= 3.3 V, CL= 50 pF +25C 01 -0.8 V Quiet output, minimum dynamic VOHVOH(V)VCC= 3.3 V, CL= 50 pF +25C 01 3.2 typical V High level dynamic input voltage VIH(D)VCC= 3.3 V, CL= 50 pF +25C 01 2.31 V Low level dynamic
29、 input voltage VIL(D)VCC= 3.3 V, CL= 50 pF +25C 01 0.99 V Operating characteristics section. Power dissipation capacitance CpdVCC= 3.3 V, CL= 50 pF, f = 10 MHz +25C 01 13.9 typical pF VCC= 5 V, CL= 50 pF, f = 10 MHz 15.4 typical 1/ Testing and other quality control techniques are used to the extent
30、deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characteriza
31、tion and/or design. 2/ Characteristics are for surface mount packages only. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 7 Case X Dimensions Symbol Milli
32、meters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 1.20 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 NOM 0.026 NOM c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 4.90 5.10 0.193 0.201 NOTES: 1. This drawing is s
33、ubject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inches). 3. Falls within JEDEC MO-153. 4. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. FIGURE 1. Case outlin
34、e. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 8 Case outlines: X Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 8 3Y 2 1B 9 3A 3
35、2A 10 3B 4 2B 11 3C 5 2C 12 1Y 6 2Y 13 1C 7 GND 14 VCCFIGURE 2. Terminal connections. ( Each gate ) Inputs Output A B C Y H H H H L X X L X L X L X X L L H = High voltage level L = Low voltage level X = Dont care FIGURE 3. Truth table. Each gate (positive logic) FIGURE 4. Logic diagram. Provided by
36、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 9 Test S1 tPLH/tPHLOpen tPLZ/tPZL VCC tPHZ/TPZH GND Open drain VCC NOTES: 1. CLincludes probe and jig capacitance. 2. Wa
37、veform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators havi
38、ng the following characteristics: PRR 1 MHz, ZO= 50 , tr 3 ns, and tf 3 ns. 4. The outputs are measured one at a time with one input transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPHLand tPLHare the same as tpd. FIGURE 5. Timing waveforms and
39、 test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04692 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for pe
40、rforming all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packagi
41、ng. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration
42、 control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of th
43、e suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Package Vendor part number Top side marking V62/04692-01XE 01295 TS
44、SOP - PW Tape and reel SN74LV11ATPWREP LV11AEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
