1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-12-08 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PR
2、EPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL, DUAL 4-BIT BINARY COUNTER, MONOLITHIC SILICON 04-04-19 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/
3、04695 REV A PAGE 1 OF 13 AMSC N/A 5962-V021-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general req
4、uirements of a high performance dual 4-bit binary counter microcircuit, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control numb
5、er for identifying the item on the engineering documentation: V62/04695 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LV393A-EP Dual 4-bit binary counter 1.2.2 Case outline(s). The ca
6、se outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MO-153 Plastic small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer. Finish designator Material A Hot solder dip B Ti
7、n-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply
8、voltage range ( VCC) . -0.5 V to 7 V Input voltage range ( VI) -0.5 V to 7 V 2/ Output voltage range applied in high or low state ( VO) -0.5 V to VCC+0.5 V 2/ 3/ Output voltage range applied in power off state ( VO) . -0.5 V to 7 V 2/ Input clamp current ( IIK) ( VI 0 ) -20 mA Output clamp current (
9、 IOK) ( VO 0 or VO VCC) . 50 mA Continuous output current ( IO) ( VO= 0 to VCC) . 25 mA Continuous current through VCCor GND . 50 mA Package thermal impedance ( JA) . 113C/W 4/ Storage temperature range (TSTG) -65C to 150C 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range ( VCC) 2 V m
10、inimum to 5.5 V maximum High level input voltage ( VIH): VCC= 2 V . 1.5 V minimum VCC= 2.3 V to 2.7 V VCCx 0.7 V minimum VCC= 3 V to 3.6 V . VCCx 0.7 V minimum VCC= 4.5 V to 5.5 V VCCx 0.7 V minimum Low level input voltage ( VIL): VCC= 2 V . 0.5 V maximum VCC= 2.3 V to 2.7 V VCCx 0.3 V maximum VCC=
11、3 V to 3.6 V . VCCx 0.3 V maximum VCC= 4.5 V to 5.5 V VCCx 0.3 V maximum Input voltage ( VI) 0 V minimum to 5.5 V maximum Output voltage ( VO) 0 V minimum to VCCmaximum High level output current ( IOH): VCC= 2 V . -50 A maximum VCC= 2.3 V to 2.7 V -2 mA maximum VCC= 3 V to 3.6 V . -6 mA maximum VCC=
12、 4.5 V to 5.5 V -12 mA maximum 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi
13、ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ This value is limited to 5.5 V maximum. 4/ The package thermal imped
14、ance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain n
15、o responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 4 1.4 Recommended operating conditi
16、ons - continued. 5/ 6/ Low level output current ( IOL): VCC= 2 V . 50 A maximum VCC= 2.3 V to 2.7 V 2 mA maximum VCC= 3 V to 3.6 V . 6 mA maximum VCC= 4.5 V to 5.5 V 12 mA maximum Input transition rise or fall rate ( t / v ): VCC= 2.3 V to 2.7 V 200 ns/V maximum VCC= 3 V to 3.6 V . 100 ns/V maximum
17、VCC= 4.5 V to 5.5 V 20 ns/V maximum Operating free-air temperature range ( TA) -40C to +105C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications
18、 for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows
19、: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operat
20、ing conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as show
21、n in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing wav
22、eforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/
23、 Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Electrical characteristics section. High level output voltage VOHIOH= -50 A, VCC= 2 V to 5.5 V -40C to 105C 01 VCC 0.1 V IOH= -2 mA, VCC= 2.3 V 2 IOH= -6 mA, VCC= 3 V 2.48 IOH= -12 mA, VCC= 4.5 V 3.8 Low level output voltage VOLIO
24、L= 50 A, VCC= 2 V to 5.5 V -40C to 105C 01 0.1 V IOL= 2 mA, VCC= 2.3 V 0.4 IOL= 6 mA, VCC= 3 V 0.44 IOL= 12 mA, VCC= 4.5 V 0.55 Input current IIVI= 5.5 V or GND, VCC= 0 to 5.5 V -40C to 105C 01 1 A Supply current ICCVI= VCCor GND, IO= 0, VCC= 5.5 V -40C to 105C 01 20 A Off current IoffVIor VO= 0 to
25、5.5 V, VCC= 0 -40C to 105C 01 5 A Input capacitance CiVI= VCCor GND, VCC= 3.3 V -40C to 105C 01 1.8 typical pF Timing requirements section. See figure 5 Pulse duration tWCLK high or low, 25C 01 5 ns VCC= 2.5 V 0.2 V -40C to 105C 5 CLR high, 25C 5 VCC= 2.5 V 0.2 V -40C to 105C 5 Setup time tSUCLR ina
26、ctive before CLK , 25C 01 6 ns VCC= 2.5 V 0.2 V -40C to 105C 6 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 6 TABLE I. Elec
27、trical performance characteristics continued. 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Timing requirements section continued. See figure 5 Pulse duration tWCLK high or low, 25C 01 5 ns VCC= 3.3 V 0.3 V -40C to 105C 5 CLR high, 25C 5 VCC= 3.3 V 0.3 V -40C to 105C 5 Setu
28、p time tSUCLR inactive before CLK , 25C 01 5 ns VCC= 3.3 V 0.3 V -40C to 105C 5 Pulse duration tWCLK high or low, 25C 01 5 ns VCC= 5 V 0.5 V -40C to 105C 5 CLR high, 25C 5 VCC= 5 V 0.5 V -40C to 105C 5 Setup time tSUCLR inactive before CLK , 25C 01 4 ns VCC= 5 V 0.5 V -40C to 105C 4 Switching charac
29、teristics section See figure 5 Maximum frequency fmaxVCC= 2.5 V 0.2 V, CL= 50 pF 25C 01 30 MHz -40C to 105C 25 Power dissipation time tpdFrom input CLK , To output QA25C 01 21.3 ns VCC= 2.5 V 0.2 V, CL= 50 pF -40C to 105C 1 24.5 From input CLK , To output QB25C 23.9 VCC= 2.5 V 0.2 V, CL= 50 pF -40C
30、to 105C 1 27.5 From input CLK , To output QC25C 26.1 VCC= 2.5 V 0.2 V, CL= 50 pF -40C to 105C 1 30 From input CLK , To output QD25C 27.8 VCC= 2.5 V 0.2 V, CL= 50 pF -40C to 105C 1 32 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
31、om IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 7 TABLE I. Electrical performance characteristics continued. 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Switching characteristics section continued. See figure 5 Prop
32、agation delay times high to low tPHLFrom input CLR, To output Qn25C 01 17.4 ns VCC= 2.5 V 0.2 V, CL= 50 pF -40C to 105C 1 20 Maximum frequency fmaxVCC= 3.3 V 0.3 V, CL= 50 pF 25C 01 45 MHz -40C to 105C 35 Power dissipation time tpdFrom input CLK , To output QA25C 01 16.7 ns VCC= 3.3 V 0.3 V, CL= 50
33、pF -40C to 105C 1 19 From input CLK , To output QB25C 19.3 VCC= 3.3 V 0.3 V, CL= 50 pF -40C to 105C 1 22 From input CLK , To output QC25C 21.5 VCC= 3.3 V 0.3 V, CL= 50 pF -40C to 105C 1 24.5 From input CLK , To output QD25C 23.2 VCC= 3.3 V 0.3 V, CL= 50 pF -40C to 105C 1 26.5 Propagation delay times
34、 high to low tPHLFrom input CLR, To output Qn25C 01 15.8 ns VCC= 3.3 V 0.3 V, CL= 50 pF -40C to 105C 18 Maximum frequency fmaxVCC= 5 V 0.5 V, CL= 50 pF 25C 01 85 MHz -40C to 105C 75 Power dissipation time tpdFrom input CLK , To output QA25C 01 10.5 ns VCC= 5 V 0.5 V, CL= 50 pF -40C to 105C 1 12 From
35、 input CLK , To output QB25C 11.8 VCC= 5 V 0.5 V, CL= 50 pF -40C to 105C 1 13.5 From input CLK , To output QC25C 13.2 VCC= 5 V 0.5 V, CL= 50 pF -40C to 105C 1 15 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND A
36、ND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 8 TABLE I. Electrical performance characteristics continued. 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max Switching characteristics section continued. See figure 5 Power dissipation time tp
37、dFrom input CLK , To output QD25C 01 14.5 ns VCC= 5 V 0.5 V, CL= 50 pF -40C to 105C 1 16.5 Propagation delay times high to low tPHLFrom input CLR, To output Qn25C 01 10.1 ns VCC= 5 V 0.5 V, CL= 50 pF -40C to 105C 1 11.5 Noise characteristics section. 2/ Quiet output, maximum dynamic VOLVOL(P)VCC= 3.
38、3 V, CL= 50 pF +25C 01 0.8 V Quiet output, minimum dynamic VOLVOL(V)VCC= 3.3 V, CL= 50 pF +25C 01 -0.8 V Quiet output, minimum dynamic VOHVOH(V)VCC= 3.3 V, CL= 50 pF +25C 01 2.8 typical V High level dynamic input voltage VIH(D)VCC= 3.3 V, CL= 50 pF +25C 01 2.31 V Low level dynamic input voltage VIL(
39、D)VCC= 3.3 V, CL= 50 pF +25C 01 0.99 V Operating characteristics section. Power dissipation capacitance CpdVCC= 3.3 V, CL= 50 pF, f = 10 MHz +25C 01 15.2 typical pF VCC= 5 V, CL= 50 pF, f = 10 MHz 17.3 typical 1/ Testing and other quality control techniques are used to the extent deemed necessary to
40、 assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design.
41、 2/ Characteristics are for surface mount packages only. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 9 Case X Dimensions Symbol Millimeters Inches Symbo
42、l Millimeters Inches Min Max Min Max Min Max Min Max A 1.20 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 NOM 0.026 NOM c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 4.90 5.10 0.193 0.201 NOTES: 1. This drawing is subject to change wi
43、thout notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inches). 3. Falls within JEDEC MO-153. 4. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. FIGURE 1. Case outline. Provided by IHSN
44、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 10 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 1 CLRnullnullnullnullnull8 2 QD2
45、 1 CLR 9 2 QC3 1 QA10 2 QB4 1 QB11 2 QA5 1 QC12 2 CLR 6 1 QD13 2 CLRnullnullnullnullnull7 GND 14 VCCFIGURE 2. Terminal connections. Inputs Function CLRnullnullnullnullnullCLR L No change L Advance to next stage X H All outputs L FIGURE 3. Truth table. Provided by IHSNot for ResaleNo reproduction or
46、networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 11 FIGURE 4. Logic diagram. FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without licens
47、e from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04695 REV A PAGE 12 Test S1 tPLH/tPHLOpen tPLZ/tPZLVCCtPHZ/tPZHGND Open Drain VCCNOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that t
